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Freescale Semiconductor
MPC5644A
Rev. 7.1, 12/2014
MPC5644A Microcontroller
Datasheet
This is the MPC5644A Datasheet set consisting of the following files:
• MPC5644A Datasheet Addendum (MPC5644A_AD), Rev. 1
• MPC5644A Datasheet (MPC5644A), Rev. 7
© Freescale Semiconductor, Inc., 2014. All rights reserved.
1 page  
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5644A
Rev. 7, Jan 2012
MPC5644A
MPC5644A Microcontroller
Data Sheet
• 150 MHz e200z4 Power Architecture core
— Variable length instruction encoding (VLE)
— Superscalar architecture with 2 execution units
— Up to 2 integer or floating point instructions per cycle
— Up to 4 multiply and accumulate operations per cycle
• Memory organization
— 4 MB on-chip flash memory with ECC and Read
While Write (RWW)
— 192 KB on-chip SRAM with standby functionality
(32 KB) and ECC
— 8 KB instruction cache (with line locking),
configurable as 2- or 4-way
— 14 + 3 KB eTPU code and data RAM
— 5 4 crossbar switch (XBAR)
— 24-entry MMU
— External Bus Interface (EBI) with slave and master
port
• Fail Safe Protection
— 16-entry Memory Protection Unit (MPU)
— CRC unit with 3 sub-modules
— Junction temperature sensor
• Interrupts
— Configurable interrupt controller (with NMI)
— 64-channel DMA
• Serial channels
— 3 eSCI
— 3 DSPI (2 of which support downstream Micro
Second Channel [MSC])
— 3 FlexCAN with 64 messages each
— 1 FlexRay module (V2.1) up to 10 Mbit/s with dual
or single channel and 128 message objects and ECC
• 1 eMIOS: 24 unified channels
• 1 eTPU2 (second generation eTPU)
— 32 standard channels
— 1 reaction module (6 channels with three outputs
per channel)
176 (24 x 24 mm)
208 (17 x 17 mm)
324 (23 x 23 mm)
• 2 enhanced queued analog-to-digital converters
(eQADCs)
— Forty 12-bit input channels (multiplexed on 2 ADCs);
expandable to 56 channels with external multiplexers
— 6 command queues
— Trigger and DMA support
— 688 ns minimum conversion time
• On-chip CAN/SCI/FlexRay Bootstrap loader with Boot
Assist Module (BAM)
• Nexus
— Class 3+ for the e200z4 core
— Class 1 for the eTPU
• JTAG (5-pin)
• Development Trigger Semaphore (DTS)
— Register of semaphores (32-bits) and an identification
register
— Used as part of a triggered data acquisition protocol
— EVTO pin is used to communicate to the external tool
• Clock generation
— On-chip 4–40 MHz main oscillator
— On-chip FMPLL (frequency-modulated phase-locked
loop)
• Up to 120 general purpose I/O lines
— Individually programmable as input, output or special
function
— Programmable threshold (hysteresis)
• Power reduction mode: slow, stop and stand-by modes
• Flexible supply scheme
— 5 V single supply with external ballast
— Multiple external supply: 5 V, 3.3 V and 1.2 V
• Packages
— 176 LQFP
— 208 MAPBGA
— 324 TEPBGA
496-pin CSP (calibration tool only)
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009–2012. All rights reserved.
5 Page 
1.4.3 eDMA
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 64 programmable channels, with minimal intervention from the host processor. The hardware
micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data
movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.
This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes
• Transfer control descriptor organized to support two-deep, nested transfer operations
• An inner data transfer loop defined by a “minor” byte transfer count
• An outer data transfer loop defined by a “major” iteration count
• Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
• One interrupt per channel, optionally asserted at completion of major iteration count
• Error termination interrupts optionally enabled
• Support for scatter/gather DMA processing
• Ability to suspend channel transfers by a higher priority channel
1.4.4 Interrupt controller
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that
all tasks which share the resource cannot preempt each other.
The INTC provides the following features:
• 9-bit vector addresses
• Unique vector for each interrupt request source
• Hardware connection to processor or read from register
• Each interrupt source can assigned a specific priority by software
• Preemptive prioritized interrupt requests to processor
• ISR at a higher priority preempts executing ISRs or tasks at lower priorities
• Automatic pushing or popping of preempted priority to or from a LIFO
• Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources
• Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.
Freescale Semiconductor
MPC5644A Microcontroller Data Sheet, Rev. 7
7
11 Page | ||
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