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PDF PI4MSD5V9545B Data sheet ( Hoja de datos )
| Número de pieza | PI4MSD5V9545B | |
| Descripción | 4 Channel I2C bus Switch | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI4MSD5V9545B/45C
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4 Channel I2C bus Switch with Interrupt Logic and Reset
Features
1-of-4 bidirectional translating multiplexer
I2C-bus interface logic;
Operating power supply voltage :1.65 V to 5.5 V
Allows voltage level translation between 1.2V,
Description
The PI4MSD5V9545B is a quad 1-of-4 bidirectional
translating switch, controlled via the I2C bus. The
SCL/SDA upstream pair fans out to four SCx/SDx
downstream pairs, or channels.
1.8V,2.5 V, 3.3 V and 5 V buses
Low standby current
Low Ron switches
Channel selection via I2C bus
Power-up with all multiplexer channels deselected
Capacitance isolation when channel disabled
No glitch on power-up
Supports hot insertion
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 8000 V HBM per JESD22-
Any individual SCx/SDx channel or combination of
channels can be selected, determined by the contents of
the programmable control register. Four interrupt inputs,
INT0 to INT3, one for each of the downstream pairs, are
provided. One interrupt output, INT, acts as an AND of
the four interrupt inputs.
An active LOW reset input allows the PI4MSD5V-
9545B to recover from a situation where one of the
downstream buses is stuck in a LOW state. Pulling the
RESET pin LOW resets the I2C bus state machine and
causes all the channels to be deselected as does the
A114, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard
internal power-on reset function.
The pass gates of the switches are constructed such
JESD78 which exceeds 100 mA
Packages offered: TSSOP-20L
that the VCC pin can be used to limit the maximum high
voltage which will be passed by the PI4MSD5V9545B.
This allows the use of different bus voltages on each pair,
so that 1.2V,1.8 V or 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional
protection. External pull-up resistors pull the bus up to
the desired voltage level for each channel. All I/O pins
Pin Configuration
are 5 V tolerant.
The PI4MSD5V9545B and PI4MSD5V9545C are
identical except for the fixed portion of the slave address.
TSSOP20
2015-07-0039
PT0536-3 8/18/15
1
1 page  
PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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Continued
Symbol Parameter
Conditions
Select inputs A0, A1,INT0, INT1,INT2,INT3
VIL LOW-level input voltage
VIH HIGH-level input voltage
IIL LOW-level input current
Ci input capacitance
INT output
VI = GND
VI = GND
IOL LOW-level output current VOL = 0.4 V
IOH HIGH-level output current
VCC
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
Note: VCC must be lowered to 0.2 V for at least 5 us in order to reset part.
Min Typ Max
Unit
-0.5
0.7Vcc
-1
3
+0.3Vcc
6
+1
5
V
V
uA
pF
3 mA
+10 uA
AC Electrical characteristics
Tamb = - 40 ºC to +85 ºC; unless otherwise specified.
Symbol
tPD[1]
INT[2]
tV_INT
tD_INT
tREJ_L
tREJ_H
RESET
Parameter
propagation delay
Conditions
from SDA to SDx,
or SCL to SCx
valid time from INTn to
INT signal
delay time from INTn to
INT inactive
LOW-level rejection time
HIGH-level rejection time
VCC
Min Typ
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1
0.5
tw(rst)L LOW-level reset time
4
trst reset time
SDA clear
500
tREC;STA
recovery time to START
condition
0
Note
[1]Pass gate propagation delay is calculated from the 20Ω typical Ron and the 15 pF load capacitance.
[2] Measurements taken with 1 kΩpull-up resistor and 50 pF load.
Max
0.3
4
2
Unit
ns
us
us
us
us
ns
ns
ns
2015-07-0039
PT0536-3 8/18/15
5
5 Page 
PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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I2C BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this time are interpreted as control signals
Figure 7: Bit Transfer
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line
while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the STOP condition (P)
Figure 8. Definition of Start and Stop Conditions
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’
Figure 9. System Configuration
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is
not limited. Each byte of 8 bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the
bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master
2015-07-0039
PT0536-3 8/18/15
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PI4MSD5V9545B.PDF ] | |
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