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PDF PI4IOE5V9557LE Data sheet ( Hoja de datos )
| Número de pieza | PI4IOE5V9557LE | |
| Descripción | 8-bit I2C-bus and SMBus I/O port | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI4IOE5V9557
8-bit I2C-bus and SMBus I/O port with reset
Features
Operation power supply voltage from 2.3V to 5.5V
8-bit I2C-bus GPIO with interrupt and reset
5V tolerant I/Os
Polarity inversion register
Active LOW Reset Pin
Low current consumption
0Hz to 400KHz clock frequency
Noise filter on SCL/SDA inputs
Power-on reset
ESD protection (4KV HBM and 1KV CDM)
Offered in three different packages:SOIC-16,
TSSOP-16 and TQFN 4x4-16
Description
The PI4IOE5V9557 provide 8 bits of General Purpose
parallel Input/Output (GPIO) expansion for I2C-
bus/SMBus applications. It includes the features such as
higher driving capability, 5V tolerance, lower power
supply, individual I/O configuration, and smaller
packaging. It provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push
buttons, LEDs, fans, etc.
The PI4IOE5V9557 consists of an 8-bit register to
configure the I/Os as either inputs or outputs, and an 8-
bit polarity register to change the polarity of the input
port register. The data for each input or output is kept in
the corresponding Input port or Output port register. All
registers can be read by the system master.
The power-on reset sets the registers to their default
values and initializes the device state machine. The
RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device,
holding the registers and I2C-bus state machine in their
default state until the RESET input is once again HIGH.
Three hardware pins (A0, A1, A2) vary the fixed
I2C-bus address and allow up to eight devices to share
the same I2C-bus/SMBus.
Pin Configuration
Figure 1: SOIC-16/TSSOP-16 ( Top View )
Figure 2: TQFN 4x4-16 ( Top view )
2015-07-0028
PT0552-2
8/18/15
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Dynamic Characteristics
Table 3: Dynamic characteristics
Symbol
Parameter
PI4IOE5V9557
8-bit I2C-bus and SMBus I/O port with reset
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Test Conditions
Standard
mode I2C
Min Max
Fast mode I2C
Unit
Min Max
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tVD;ACK[1]
tHD;DAT[2]
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data valid acknowledge time
data hold time
tVD;DAT data valid time
tSU;DAT data set-up time
tLOW LOW period of the SCL clock
tHIGH HIGH period of the SCL clock
tf fall time of both SDA and SCL signals
tr rise time of both SDA and SCL signals
tSP
pulse width of spikes that must be
suppressed by the input filter
Port timing
0 100
4.7 -
4.0 -
4.7 -
4.0 -
- 3.45
0-
- 3.45
250 -
4.7 -
4.0 -
- 300
- 1000
- 50
0
1.3
0.6
0.6
0.6
-
0
-
100
1.3
0.6
-
-
-
400 kHz
- μs
- μs
- μs
- μs
0.9 μs
- ns
0.9 us
- ns
- μs
- μs
300 ns
300 ns
50 ns
tv(Q) Data output valid time[3]
Pin IO0
Pin IO1 to IO7
- 250 - 250 ns
- 200 - 200 ns
tsu(D) Data input set-up time
th(D) Data input hold time
Reset timing
0 - 0 - ns
200 - 200 - ns
tw(rst)
trec(rst)
trst
Reset pulse width
Reset recovery time
Reset time
25 - 25 - ns
0 - 0 - ns
1 - 1 - us
2015-07-0028
PT0552-2
8/18/15
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Figure 9: Read input port register
PI4IOE5V9557
8-bit I2C-bus and SMBus I/O port with reset
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Note: This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge
phase is valid (output mode). Input data is lost.
Application design-in information
Figure 10: Typical application
Device address configured as 0011100x for this example.
IO0, IO4, IO5 configured as outputs.
IO1, IO2, IO3 configured as inputs.
IO6, IO07 are not used.
2015-07-0028
11
PT0552-2
8/18/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet PI4IOE5V9557LE.PDF ] | |
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