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PDF SS2412 Data sheet ( Hoja de datos )

Número de pieza SS2412
Descripción CMOS High Sensitivity Micropower Hall Latch
Fabricantes SEC 
Logotipo SEC Logotipo



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SS2412
CMOS High Sensitivity Micropower Hall Latch
Features and Benefits
Micropower consumption for battery pow-
ered applications
Latching output
Operation down to 2.5V
High sensitivity for direct reed switch re-
placement applications
Chopper stabilized amplifier stage
Application Examples
Solid state switch
Handheld Wireless Handset Awake Switch
Lid close sensor for battery powered devices
3 pin SOT23 (suffix SO)
3 pin SIP (suffix UA)
Functional Block Diagram
VDD
Sleep/Awake
Li
OUT
Chopper
Hall
GND
1 V3.10 Nov 1, 2013

1 page




SS2412 pdf
SS2412
CMOS High Sensitivity Micropower Hall Latch
Output Behavior versus Magnetic Pole
DC Operating Parameters TA = -40°C to 150°C, VDD = 2.5 to 5.5V (unless otherwise specified)
Test Conditions (UA) Test Conditions (SO) OUT
B < BRP
B > BRP
High
B > BOP
B < BOP
Low
The SOT-23 device is reversed from the UA package. The SOT-23 output transistor will be turned on(drops low) in the presence of a
sufficiently strong North pole magnetic field applied to the marked face and turned off(hoists high) in the presence of a sufficiently
strong South pole magnetic field.
Unique Features
CMOS Hall IC Technology
The chopper stabilized amplifier uses switched capacitor techniques to eliminate the amplifier offset voltage,
which, in bipolar devices, is a major source of temperature sensitive drift. CMOS makes this advanced technique
possible. The CMOS chip is also much smaller than a bipolar chip, allowing very sophisticated circuitry to be
placed in less space. The small chip size also contributes to lower physical stress and less power consumption.
ESD Protection
Human Body Model (HBM) tests according to: Mil. Std. 883F method 3015.7
Parameter
Symbol
Limit Values
Min Max
Unit
ESD Voltage
VESD
±4 kV
Notes
ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static
Discharge control procedures whenever handling semiconductor products.
5 V3.10 Nov 1, 2013

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