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PDF CPC5601 Data sheet ( Hoja de datos )
| Número de pieza | CPC5601 | |
| Descripción | Auxiliary Programmable Driver IC | |
| Fabricantes | IXYS | |
| Logotipo |  |
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INTEGRATED CIRCUITS DIVISION
Features
• Meets PC Card (PCMCIA) height requirements
• Zero standby current
• PCB real estate and cost savings
• Can be used with LITELINK II and LITELINK III parts
Compliance
• TIA/EIA/IS-968 (FCC part 68)
• UL1950
• UL60950
• EN/IEC 60950-1 compliant
• EN55022B
• CISPR22B
• EN55024
• TBR-21
Ordering Information
Part Number Description
CPC5601D
16-pin, 14-lead SOIC, 0.300” wide package,
50/Tube
CPC5601DTR
16-pin, 14-lead SOIC, 0.300” wide package,
1000/Reel
Figure 1. CPC5601 Block Diagram
RING 1
GND 2
INPUT 3
NC 6
Shift
Register
Drivers
16 LED-
15 LED+
14 VDDLINE
13
12
11
10
9
8
B1
B2
B3
B4
B5
B6
7 -BR
CPC5601 LITELINK™ Family
Auxiliary Programmable Driver IC
Description
The CPC5601 is a serially-programmed driver IC for
use with IXYS Integrated Circuits Division’s LITELINK
Silicon Data Access Arrangement (DAA) ICs. The
CPC5601 allows host-equipment control of DAA char-
acteristics for worldwide DAA implementations, avoid-
ing multiple implementations with discrete component
changes or “stuff” options. The small, low-profile pack-
age makes the CPC5601 ideal for 56K PC Card
(PCMCIA) modems, PC motherboards, and soft-
modems.
The CPC5601 uses opto-electronics to maintain the
isolation barrier required in the data access arrange-
ment for connection of host devices to the public
switched telephone network (PSTN).
The one-bit serial input of the CPC5601 recovers
clocking information from the input signal to set bits in
the shift register. The shift register outputs connect to
open-drain FET latches that are used to switch in dif-
ferent external components to set V/I slope, DC termi-
nation current limit, gain, and AC termination value in
LITELINK DAA implementations.The CPC5601 does
not need a clock signal for shift register operation, but
relies on internal timing instead.
The CPC5601 also includes an opto-coupler for ring
detection applications where the AC coupled ring
detector of the LITELINK DAA is not used.
Pb e3
DS-CPC5601-R04
www.ixysic.com
1
1 page  
INTEGRATED CIRCUITS DIVISION
2. Application
In the application circuits shown below, the CPC5601
is used to switch AC termination and gain. Loop-cur-
rent limit switching is optional.
Figure 3. CPC5601 Application Circuit Using the LITELINK II and the Optical Snoop Circuit
CPC5601
C3 0.1
II
REFM
R77 499K 1%
501K
0.015
301
¹This design was tested and found to comply with FCC part 68 with this part.
Other compliance requirements may require a different part.
²Higher noise power supplies may require substitution of a 220 H inductor,
Toko 380HB-2215 or similar. See the power quality section of Clare applica-
tion note AN-146, Guidelines for Effective LITELINK Designs for more informa-
tion. Both application circuits use the same components for setting AC
termination and the telephone line current limit.
3Addition of this capacitor improves trans-hybrid loss.
R04 www.ixysic.com
5
5 Page 
INTEGRATED CIRCUITS DIVISION
CPC5601
3.2 Programming Protocol
Figure 5. Latch Circuit Timing to Turn an Output On
INPUT (pin 3)
t0
>=50s (tsetup)
CLOCK
200s
140s
thold
Transition after setup time
initiates clock pulse
B1 (pin 13)
B1 output FET (drain open)
First reads data
at the rising edge of the clock
A setup pulse on the input of at least 50 S starts the
bit programming sequence. The trailing edge of the
setup pulse starts a timer on the CPC5601 (t0). After
140 S, the value of the input is latched into the shift
register.
B1 output FET on (sinking current)
To set an output, hold the input high for 200 S from
the leading edge after the setup pulse. This turns on
the corresponding open-drain FET to sink current.
Figure 6. Latch Circuit Timing to Turn an Output Off
INPUT (pin 3)
t0
>=50 s (tsetup) 50 s
140 s
150 s min
CLOCK
Transition after setup time
initiates clock pulse
First reads data
at the rising edge of the clock
B1 (pin 13)
B1 output FET on (sinking current)
B1 output FET (drain open)
To clear an output, hold the input high for 50 S after
the setup pulse, then take the input low for at least 150
S.
Repeat the sequence of the setup pulse followed by
the appropriate input condition for each successive bit.
Bear the following in mind while programming the
CPC5601:
• All bits must be set in each programming sequence,
even to change just one of the outputs.
• Data is placed in least-significant bit (output 1) first.
• After setting all the bits, take the input low. In the
absence of low-to-high transitions on the input, the
internal CPC5601 clock is held high, preventing any
output changes.
• The CPC5601 does not employ a shift register load
function. As new data is shifted into the flip-flops, the
outputs (starting with b1) change throughout the
data input sequence.
3.3 Programming Example
This programming example sets the following
CPC5601 output state, suitable for a European DAA:
R04 www.ixysic.com
11
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CPC5601.PDF ] | |
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