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PDF CDP68HC68T1 Data sheet ( Hoja de datos )
| Número de pieza | CDP68HC68T1 | |
| Descripción | CMOS Serial Real-Time Clock | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
CDP68HC68T1
October 29, 2007
FN1547.8
CMOS Serial Real-Time Clock With RAM
and Power Sense/Control
The CDP68HC68T1 Real-Time Clock provides a
time/calendar function, a 32 byte static RAM, and a 3 wire
Serial Peripheral Interface (SPI Bus). The primary function of
the clock is to divide down a frequency input that can be
supplied by the on-board oscillator in conjunction with an
external crystal or by an external clock source. The internal
oscillator can operate with a 32kHz, 1MHz, 2MHz, or 4MHz
crystal. An external clock source with a 32kHz, 1MHz, 2MHz,
4MHz, 50Hz or 60Hz frequency can be used to drive the
CDP68HC68T1. The time registers hold seconds, minutes,
and hours, while the calendar registers hold day-of-week,
date, month, and year information. The data is stored in BCD
format. In addition, 12 or 24 hour operation can be selected.
In 12 hour mode, an AM/PM indicator is provided. The T1
has a programmable output which can provide one of seven
outputs for use elsewhere in the system.
Computer handshaking is controlled with a “wired-OR” interrupt
output. The interrupt can be programmed to provide a signal as
the result of:
1. An alarm programmed to occur at a predetermined
combination of seconds, minutes, and hours.
2. One of 15 periodic interrupts ranging from sub-second to
once per day frequency.
3. A power fail detect. The PSE output and the VSYS input are
used for external power control. The CPUR output is
available to reset the processor under power-down
conditions. CPUR is enabled under software control and
can also be activated via the CDP68HC68T1’s watchdog. If
enabled, the watchdog requires a periodic toggle of the CE
pin without a serial transfer.
Pinouts
CDP68HC68T1
(16 LD PDIP, SOIC)
TOP VIEW
CLKOUT 1
CPUR 2
INT 3
SCK 4
MOSI 5
MISO 6
CE 7
VSS 8
16 VDD
15 XTAL OUT
14 XTAL IN
13 VBATT
12 VSYS
11 LINE
10 POR
9 PSE
Features
• SPI (Serial Peripheral Interface)
• Full Clock Features
- Seconds, Minutes, Hours (12/24, AM/PM), Day of
Week, Date, Month, Year (0 to 99), Automatic Leap Year
• 32 Wordx8-Bit RAM
• Seconds, Minutes, Hours Alarm
• Automatic Power Loss Detection
• Low Minimum Standby (Timekeeping) Voltage . . . . . 2.2V
• Selectable Crystal or 50/60Hz Line Input
• Buffered Clock Output
• Battery Input Pin that Powers Oscillator and also
Connects to VDD Pin When Power Fails
• Three Independent Interrupt Modes
- Alarm
- Periodic
- Power-Down Sense
• Pb-Free Available (RoHS Compliant)
CDP68HC68T1
(20 LD SOIC)
TOP VIEW
CLK OUT 1
CPUR 2
INT 3
NC 4
SCK 5
MOSI 6
MISO 7
CE 8
VSS 9
PSE 10
20 VDD
19 XTAL OUT
18 XTAL IN
17 NC
16 VBATT
15 VSYS
14 NC
13 NC
12 LINE
11 POR
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1997. Copyright Intersil Americas Inc. 2001, 2004-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Functional Block Diagram
CE
LINE
XTAL IN
XTAL OUT
VBATT
CLOCK
OUT
INT
VDD
VSS
50/60Hz
OSCILLATOR
FREEZE
CIRCUIT
PRESCALE
SECOND
PRESCALE
SELECT
CLOCK
SELECT
CLOCK
AND
INT
LOGIC
CLOCK
CONTROL
REGISTER
INTERRUPT
CONTROL
REGISTER
LINE
VSYS
POR
PSE
CPUR
SCK
MISO
MOSI
POWER
SENSE
CONTROL
INT STATUS
REGISTER
SERIAL
INTERFACE
AM - PM AND
HOUR LOGIC
MINUTE
HOUR
CALENDAR
LOGIC
DAY/DAY
OF WEEK
8-BIT DATA BUS
SECOND
LATCH
COMPARATOR
MINUTE
LATCH
HOUR
LATCH
32x8
RAM
FIGURE 1. REAL TIME CLOCK FUNCTIONAL DIAGRAM
MONTH
YEAR
5 Page 
CDP68HC68T1
XTAL
IN
T1
22M
XTAL
OUT
5pF TO 30pF
C1
10pF TO 40pF
C2
NOTES:
7. All frequencies recommended oscillator circuit. C1, C2 values
crystal dependent.
8. R is used for 32KHz operation only. 100k to 300k range as
specified by crystal manufacturer.
FIGURE 7. OSCILLATOR CIRCUIT
VSYS
This input is connected to the system voltage. After the CPU
initiates power down by setting Bit 6 in the Interrupt Control
Register to “1”, the level on this pin will terminate power
down if it rises about 1.0V above the level at the VBATT input
pin after previously falling below VBATT +1.0V. When
power-down is terminated, the PSE pin will return high and
the Clock Output will be enabled. The CPUR output pin will
also return high. The logic level present at this pin at the end
of POR determines the CDP68HC68T1’s operating mode.
VBATT
The oscillator power source. The positive terminal of the
battery should be connected to this pin. When the level on
the VSYS pin falls below VBATT +1.0V, the VBATT pin will be
internally connected to the VDD pin. When the voltage on
VSYS rises a threshold above (1.0V) the voltage on VBATT,
the connection from VBATT to the VDD pin is opened. When
the “LINE” input is used as the frequency source, VBATT
may be tied to VDD or VSS. The “XTAL IN” pin must be at
VSS if VBATT is at VSS. If VBATT is connected to VDD, the
“XTAL IN” pin can be tied to VSS or VDD.
XTAL IN, XTAL OUT
These pins are connected to a 32,768Hz. 1.048576MHz,
2.097152MHz or 4.194304MHz crystal. If an external clock
is used, it should be connected to “XTAL IN” with ‘XTAL
OUT” left open.
VDD
The positive power-supply pin.
Clock Control Register
Start-Stop
A high written into this bit will enable the counter stages of
the clock circuitry. A low will hold all bits reset in the divider
chain from 32Hz to 1Hz. A clock out selected by Bit 0, Bit 1
and Bit 2 will not be affected by the stop function except the
1Hz and 2Hz outputs.
Line-XTAL
When this bit is set high, clock operation will use the
50-cycle or 60-cycle input present at the LINE input pin.
When the bit is low, the crystal input will generate the 1Hz
time update.
XTAL Select
One of 4 possible crystals is selected by value in these two
bits:
0 = 4.194304MHz 2 = 1.048576MHz
1 = 2.097152MHz 3 = 32,768Hz
50Hz to 60Hz
50Hz is selected as the line input frequency when this bit is
set high. A low will select 60Hz. The power-sense bit in the
Interrupt Control Register must be set low for line frequency
operation.
Clock Out
The three bits specify one of the 7 frequencies to be used as
the squarewave clock output:
0 = XTAL
1 = XTAL/2
2 = XTAL/4
3 = XTAL/8
4 = Disable (low output)
5 = 1Hz
6 = 2Hz
7 = 50Hz or 60Hz
XTAL Operation = 64Hz
All bits are reset by a power-on reset. Therefore, the XTAL is
selected as the clock output at this time.
Interrupt Control Register
Watchdog
When this bit is set high, the watchdog operation will be
enabled. This function requires the CPU to toggle the CE pin
periodically without a serial-transfer requirement. In the
event this does not occur, a CPU reset will be issued. Status
Register must be read before re-enabling watchdog.
Power-Down
A high in this location will initiate a power down. A CPU reset
will occur, the CLK OUT and PSE output pins will be set low
and the serial interface will be disabled.
Power Sense
This bit is used to enable the line input pin to sense a power
failure. It is set high for this function. When power sense is
selected, the input to the 50Hz to 60Hz prescaler is
disconnected. Therefore, crystal operation is required when
power sense is enabled. An interrupt is generated when a
power failure is sensed and the power sense and Interrupt
True bit in the Status Register are set. When power sense is
activated, a “0” must be written to this location followed by a
“1” to re-enable power sense.
11 FN1547.8
October 29, 2007
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet CDP68HC68T1.PDF ] | |
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