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PDF RTM660-110R Data sheet ( Hoja de datos )

Número de pieza RTM660-110R
Descripción Clock Generator
Fabricantes RealTek 
Logotipo RealTek Logotipo



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No Preview Available ! RTM660-110R Hoja de datos, Descripción, Manual

Clock Generator
General Description
The RTM660-110R is a single chip frequency generator for INTEL CK Titan Clock Synthesizer
Driver Specification. The clock chip provides standard serial bus for programming device function.
Base on the function above, the spread spectrum can be enable for reducing EMI.
Features
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Support Up to 266 MHz frequency.
Power Down feature.
Programmable Spread Spectrum depth.
Programmable Spread Spectrum model.
Programmable driving strength.
Programmable skew delay.
Programmable PLL frequency.
Programmable Loop Filter.
Programmable Smooth-Divider.
Programmable current Iref.
Programmable current Vg( Vref).
Programmable Watch Dog & Smooth
Reset circuit.
DOS/WIN9x/WIN2000/WINNT AP.
Enhance 266/233/200/166/133/100/66
CPU frequency ratio.
Mult-1*/REF 1
VDD_3.3
X1
X2
GND
FS2*/PCIF - 0
FS3*/PCIF - 1
ENWD#*/PCIF - 2
VDD_3.3
FS4*/PCI - 0
FS5**/PCI - 1
PCI - 2
GND
PCI - 3
PCI - 4
PCI - 5
PCI - 6
VDD_3.3
Vtt_Power_Good #
RESET #
GND
FS0*/48Mhz
FS1*/24_48#Mhz
VDD_3.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 Mult-0*/REF 0
47 GND
46 VDD_3.3
45 CPU-0
44 CPU-0 #
43 GND
42 PD #*
41 CPU-1
40 CPU-1 #
39 VDD_3.3
38 CPU-2
37 CPU-2 #
36 GND
35 Iref
34 VDD_3.3_CORE
33 GND_CORE
32 VDD_3.3
31 3V66 - 0
30 3V66 - 1
29 GND
28 3V66 - 2
27 3V66 - 3
26 SCLK
25 SDATA
Sdata
Sclk standard serial
bus
FS0..FS5
Mult0..1
ROM
PD#
PWRGD#
Digital
control
XTAL
PLL2
PLL1
Current
PAD
CPU0..2
CPU#0..2
IREF
Divider
&
Muxer
Delay
&
Stop
Buffer
&
Strength
control
REF0..1
PCIF0..2
PCI0..6
3V660..3
24/48 MHz
48 MHz
01/05/18
-1-

1 page




RTM660-110R pdf
Register Description
Clock Generator
CR 00h
Bit
Bit7
Bit6
Bit5=0
Bit4
Bit3
Bit2
Bit1
Bit0
Description
0 = frequency is selected by latched input FS[5:0]
1 = frequency is selected by CR07h – bit 5, 4, 3, 2, 1, 0
0 = spread spectrum disable
1 = spread spectrum enable
Bit4 Bit3
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
Bit2 Bit1 Bit0 CPU
0 0 0 102.00
0 0 1 105.00
0 1 0 108.00
0 1 1 111.00
1 0 0 114.00
1 0 1 117.00
1 1 0 120.00
1 1 1 123.00
0 0 0 126.00
0 0 1 130.00
0 1 0 136.00
0 1 1 140.00
1 0 0 144.00
1 0 1 148.00
1 1 0 152.00
1 1 1 156.00
0 0 0 160.00
0 0 1 164.00
0 1 0 166.60
0 1 1 170.00
1 0 0 175.00
1 0 1 180.00
1 1 0 185.00
1 1 1 190.00
0 0 0 66.80
0 0 1 100.20
0 1 0 200.40
0 1 1 133.60
1 0 0 66.60
1 0 1 100.00
1 1 0 200.00
1 1 1 133.30
Ratio
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.50
2.50
2.50
2.50
2.50
2.50
1.00
1.50
3.00
2.00
1.00
1.50
3.00
2.00
3V66
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
84.00
86.67
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
66.64
68.00
70.00
72.00
74.00
76.00
66.80
66.80
66.80
66.80
66.60
66.67
66.67
66.65
Note1: Default at power-up will be for latched logic inputs to define frequency, Bit 5:0 are default to 000000.
Default
0
0
PCI
34.00
0
35.00
0
36.00
37.00
0
38.00
39.00
0
40.00
41.00
42.00
0
0
43.33
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
33.32
34.00
35.00
36.00
37.00
38.00
33.40
33.40
33.40
33.40
33.30
33.33
33.33
33.33
01/05/18
-5-

5 Page





RTM660-110R arduino
Clock Generator
Power Down Function
PD# CPU CPU# 3V66 PCI-F PCI REF 48 24/48 Osc VCOs
Itotal
0 Iref*2 float Low Low Low Low Low Low Off Off 25/45 mA
1 On
On
On
On On On On On On On 280 mA
Power Down Waveform
10 ns
PD#
CPU 100MHz
CPU# 100MHz
3V66 66MHz
posedge 1 posedge 2
waiting posedge & negedge
negedge 1
posedge 1 negedge 1
posedge 1 negedge 1
PCI 33MHz
REF 14.318MHz
48MHz 48MHz
posedge 1
negedge 1
posedge 1
posedge 1
negedge 1
negedge 1
Note
1. After PD# is sampled active (Low) for 2 consecutive rising edges of CPUCLK#, all the output clocks are driven Low on their next High to Low transition.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
01/05/18
- 11 -

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