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Número de pieza | AK4360 | |
Descripción | Low Power 2ch DAC | |
Fabricantes | Asahi Kasei Microsystems | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AK4360 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
No Preview Available ! ASAHI KASEI
[AK4360]
AK4360
Low Power 2ch ∆Σ DAC with HP-AMP
GENERAL DESCRIPTION
The AK4360 is a 20bit low voltage & power DAC with Headphone Amplifier for digital audio system. The
AK4360 uses the new developed Multi-Bit ∆Σ architecture, this new architecture achieves S/N=92dB at
low voltage operation. The AK4360 integrates SCF increasing performance for systems with excessive
clock jitter. The low power and small package make this point ideal for the portable audio system like MD,
MP3, etc.
FEATURES
• Advanced Multi-Bit ∆Σ DAC
• Sampling Rate Ranging: 8kHz ∼ 50kHz
• On chip perfect filtering 8 times FIR interpolator
• Digital de-emphasis for 44.1kHz sampling
• Master clock: 256fs or 384fs
• Digital Audio I/F Format: 2’s compliment, MSB first
- 20bit I2S or 16bit LSB justified
• THD+N: -48dB (-11dB output)
• D-Range, S/N: 92dB
• Low Frequency Boost Function
• Click Noise Free Circuit
• On chip Headphone Amplifier
- 6.5mW x 2ch@16Ω (THD+N = 10%, HPVCC = 1.2V)
• Low Voltage Operation: DAC: 2V (1.8V∼3.3V), HP-AMP: 1.2V (0.9V∼3.3V)
• Low power Dissipation: 12mW
• Ta = -10 ∼ 70°C
• Small Package: 24pin VSOP
DIF
DEM
HPVCC HPGND
BICK
LRCK
SDATA
Audio
I/F
De-emphasis
Control
Voltage
Reference
VREF
VCOM
BOOST
VDD
VSS
Low
Freq
Boost
8X
Interpolator
8X
Interpolator
∆Σ
Modulator
∆Σ
Modulator
SCF
HP-AMP
SCF
HP-AMP
Clock Divider
Mute Circuit
AOUTL
AOUTR
PDN
MCLK CKS
MT0 MT1 MUTEN
MS0072-E-00
-1-
2001/01
1 page ASAHI KASEI
[AK4360]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=2.0V, HPVCC=1.2V, VSS=HPGND=0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz;
Measurement frequency=10Hz ∼ 20kHz; Load impedance is a serial connection with RL =16Ω and CL=220µF;
unless otherwise specified)
Parameter
min typ max Units
Headphone Output Dynamic Characteristics: (Note 3)
THD+N
(0dB Output, 6.5mW)
-20 - dB
(-11dB Output, 0.5mW)
-48 -40 dB
(-30dB Output)
-60 - dB
Dynamic Range (-60dB Output, A-weight)
86 92
dB
S/N (A-weight)
86 92
dB
Interchannel Isolation
75 90
dB
DC Accuracy
Interchannel Gain Mismatch
0.3 0.5 dB
Gain Drift
- 200 - ppm/°C
Output Voltage (-11dB Output)
0.25 0.275 0.3 Vpp
Load Resistance
16 Ω
Power Supplies
Power Supply Current
Normal Operation (PDN = MUTEN= “H”)
VDD
HPVCC (Digital “0” Data Input)
4.0 6.0 mA
3.4 6.5 mA
Power-Down Mode (PDN = MUTEN= “L”)
VDD+HPVCC
(Note 4)
10 100 µA
Power Supply Rejection
(Note 5)
- 50 - dB
Note 3. Measured by Audio Precision, System Two.
Note 4. In case of power-down mode (PDN = MUTEN = “L”), all digital input pins including clock pins (MCLK, BICK
and LRCK) are held VDD or VSS.
Note 5. PSR is applied to VDD with 1kHz, 100mVpp.
MS0072-E-00
-5-
2001/01
5 Page ASAHI KASEI
n Power Up/Down Sequence
[AK4360]
VDD pin
HPVCC pin
PDN pin
(1)
(4)
MUTEN pin
(4)
Clock In
MCLK, BICK, LRCK
(6)
(3)
(2)
(5)
(6)
Notes:
(1) HPVCC and VDD pins should be powered-up at the same time or HPVCC pin should be powered-up
earlier than VDD pin.
(2) VDD pin should be powered-down passed by more than 30ms after PDN pin = “L”.
(3) HPVCC and VDD pins should be powered-down at the same time or VDD pin should be powered-down
earlier than HPVCC pin.
(4) PDN and MUTEN pins should be “L” as the click noise occurs at power-up.
(5) HP-Amp outputs should be muted by MUTEN pin = “L” before power-down.
(6) In case of PDN pin = MUTEN pin = “L”, the clock may be stopped.
Figure 7. Power Up/Down Sequence example
MS0072-E-00
- 11 -
2001/01
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet AK4360.PDF ] |
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