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PDF AK4101A Data sheet ( Hoja de datos )
| Número de pieza | AK4101A | |
| Descripción | Quad Outputs 192kHz 24-Bit DIT | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4101A]
AK4101A
Quad Outputs 192kHz 24-Bit DIT
GENERAL DESCRIPTION
The AK4101A is a four outputs digital audio transmitter (DIT) which supports data rate up to 192kHz
sample rate operation. The AK4101A supports AES3, IEC60958, S/PDIF & EIAJ CP1201 interface
standards. The AK4101A accepts audio data and auxiliary information data and etc, which is then
biphase-encoded and driven on to a cable. The audio serial port supports eight formats.
o Sampling Rate up to 192kHz
FEATURES
o Support AES3, IEC60958, S/PDIF & EIAJ CP1201 professional and consumer formats
o Generates CRCC codes and parity bits
o Four on-chip RS422 line drivers
o 64-byte on-chip buffer memory for Channel Status and User bits
o Supports synchronous/asynchronous access to Channel Status and User bits
o Supports multiple clock frequencies: 128fs, 256fs, 384fs and 512fs
o Supports Left/Right justified and I2S audio formats
o Easy to use 4 wire, Serial Host Interface
o Audio Routing Mode (Transparent Mode)
o Power supply: 4.75 to 5.25V
o TTL level I/F
o Small Package: 44pin LQFP
o Temperature range of - 40 to 85 °C
MS0250-E-00
-1-
2003/07
1 page  
ASAHI KASEI
[AK4101A]
No. Pin Name
I/O
Description
23 CKS1
I Clock Mode Select 1 Pin
(Pull-down Pin)
24 TXN4
O Negative Differential Output Pin for Channel 4
25 TXP4
O Positive Differential Output Pin for Channel 4
26 TXN3
O Negative Differential Output Pin for Channel 3
27 TXP3
O Positive Differential Output Pin for Channel 3
28 VDD
- Power Supply Pin, 4.75V∼5.25V
29 VSS
- Ground Pin, 0V
30 TXN2
O Negative Differential Output Pin for Channel 2
31 TXP2
O Positive Differential Output Pin for Channel 2
32 TXN1
O Negative Differential Output Pin for Channel 1
33 TXP1
O Positive Differential Output Pin for Channel 1
34 DIF0
I Audio Serial Interface Select 0 Pin
(Pull-down Pin)
35 VDD
- Power Supply Pin, 4.75V∼5.25V
36 DIF1
I Audio Serial Interface Select 1 Pin
(Pull-down Pin)
37 DIF2
I Audio Serial Interface Select 2 Pin
(Pull-down Pin)
38 U1
I User Data Bit Input Pin for Channel 1
(Pull-down Pin)
39 U2
I User Data Bit Input Pin for Channel 2
(Pull-down Pin)
40 U3
I User Data Bit Input Pin for Channel 3
(Pull-down Pin)
41 U4
I User Data Bit Input Pin for Channel 4
(Pull-down Pin)
42 V12
I Validity Bit Input Pin for Channel 1 & Channel 2
43 V34
I Validity Bit Input Pin for Channel 3 & Channel 4 (Pull-down Pin)
44 TRANS
I Audio Routing Mode (Transparent Mode) Pin at Synchronous mode
0: Normal mode, 1: Audio routing mode (Transparent mode)
Notes:
1. Internal pull-up and pull-down resistors are connected on-chip. The value of the resistors is 43kΩ (typ).
2. All input pins except internal pull-down/pull-up pins should not be left floating.
MS0250-E-00
-5-
2003/07
5 Page 
ASAHI KASEI
[AK4101A]
OPERATION OVERVIEW
n General Description
The AK4101A is a monolithic CMOS circuit that biphase-encodes and transmits audio data, auxiliary information data
and etc according to the AES3, IEC60958, S/PDIF and EIAJ CP1201 interface standards. There are four sets of stereo
channels that can be transmitted simultaneously. The chip accepts audio data and auxiliary information data separately,
multiplexes and biphase-mark encodes the data internally, and drives it directly or through a transformer to a
transmission line. There are two modes of operation: asynchronous and synchronous. See section of “Asynchronous
Mode/ Synchronous Mode”.
n Initialization
The AK4101A takes 8 bit clock cycles to initialize after PDN pin goes inactive. Also, for correct synchronization,
MCLK should be synchronized with LRCK but the phase is not critical.
n MCLK and LRCK Relationship
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through
a frequency divider) or indirectly (for example, as through a DSP). The relationship of BICK to LRCK is fixed and
should not change. If MCLK or LRCK move such that they are shifted (128fs x 3) or more cycles from their initial
conditions, the chip will reset the internal frame and bit counters. However, control registers are not initialized. The
following frequencies are supported for MCLK.
CKS1
0
0
1
1
CKS0
0
1
0
1
MCLK
128fs
256fs
384fs
512fs
fs
28k-192kHz
28k-108kHz
28k-54kHz
28k-54kHz
Table 1. MCLK Frequency
n Asynchronous Mode/ Synchronous Mode
1. Asynchronous Mode (software controlled)
The AK4101A can be configured in the asynchronous mode by connecting the ANS pin to logic “L”. In this mode the
16 to 24-bit audio samples are accepted through a configured audio serial port, and the channel status and user data
through a serial control host interface (SCI). The SCI allows access to internal buffer memory and control registers
which are used to store the channel status and user data. 4bytes per channel of user and channel status is stored. This
data is multiplexed with the audio data from the audio serial port, the parity bit is generated, and the bit stream is
biphase-mark encoded and driven through the RS422 line drivers. The CRCC code for the channel status is also
generated according to the professional mode definition in the AES3 standards. This mode also allows for software
control for mute, reset, audio format selection, clock frequency settings and output enables, via the serial host interface.
MS0250-E-00
- 11 -
2003/07
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AK4101A.PDF ] | |
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