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PDF GPCE2P064A Data sheet ( Hoja de datos )
| Número de pieza | GPCE2P064A | |
| Descripción | 16-bit Sound Controller | |
| Fabricantes | Generalplus | |
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GPCE2P064A
16-bit Sound Controller with
32K X 16 OTP
Jun 02, 2016
Version 1.4
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
1 page  
GPCE2P064A
5 SIGNAL DESCRIPTIONS
Mnemonic
PORT A, Port B
IOA[15:0]
PIN No.
66-69, 1-4, 7-14
IOB [15:0]
52-45, 42-35
Power & GND
VDD_IOA
5
VSS_IOA
6
VDD_IOB
43
VSS_IOB
44
V33_ADC
27
VSS_ADC
26
V33_REG
16
VDD_REG
15
VSS_REG
18
VDD_DAC
59
VDD_PDAC
57, 58
VSS_DAC
64
VSS_ PDAC
53, 54, 62, 63
CLK SYSTEM/ ICE INTERFACE
XTI 24
XTO
23
OPTION
TEST
25
VPP
EPM
R32SEL
DAC
AUDP
AUDN
ACIN
ADC
MICP
MICN
MICOUT
OPI
AGC
VMIC
VADREF
PLL
VCOIN
17
20
19
60, 61
55, 56
65
34
33
32
31
30
28
29
21
© Generalplus Technology Inc.
Proprietary & Confidential
Type
Description
I/O IOA[15:0]: bi-directional I/O ports
It can be programmed as wakeup I/O pins
I/O IOB [15:0]: bi-directional I/O ports
IOB[15] is shared with OTP_SDA (OTP programming data)
IOB[14] is shared with OTP_SCK (OTP programming clock)
P Power VDD for Port A
G Power GND for Port A
P Power VDD for Port B
G Power GND for Port B
P Power VDD for AD(3.3V)
G Power GND for AD
P 3V power output from regulator
P Positive supply for regulator(2.4V~5.5V)
G Ground reference for regulator
P Positive 5V supply for push-pull DAC
P Positive 5V supply for push-pull DAC post driver
I Ground reference for push-pull DAC
I Ground reference for push-pull DAC post driver
I 32KHz Oscillator crystal input
O 32KHz Oscillator crystal output
I TEST Mode selection pin, high is test mode and low is normal mode (Pad
internal pull low)
I High voltage input for OTP programming use, keep it floating in normal run.
I Connect it to VDD during OTP programming cycle, keep it floating in normal run.
R32K or Xtal32K select. Connected to VSS when Xtal32K is selected, and
I
connected to V33_REG when R32K is selected.
O Audio output of push pull DAC
O Audio output of push pull DAC
U Audio analog mixer in
I MIC amplifier input positive (Internal Floating)
I MIC amplifier input negative (refer to application circuit)
O MIC amplifier output (refer to application circuit)
I Audio amplifier negative input (refer to application circuit)
IO AGC by pass filter (refer to application circuit)
O Microphone power supply
O AVREF_DA reference pin
I PLL low pass filter input
5 Jun 02, 2016
Version: 1.4
5 Page 
GPCE2P064A
TMXSEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TimerA_Timeout
PWMO
Input 1
‘0’
‘1’
FRTC
FPLL
EXT2
EXT2
EXT2
EXT2
FRTC
FRTC
FRTC
FRTC
FPLL
FPLL
FPLL
FPLL
Input 2
‘0’
‘1’
EXT2
EXT2
64Hz
16Hz
2Hz
‘1’
64Hz
16Hz
2Hz
‘1’
64Hz
16Hz
2Hz
‘1’
The following clock source A/B/C means clock source for Timer
A/B/C respectively. Generally speaking, the clock source A and
C are fast clock sources and source B comes from RTC system
(32768Hz). Therefore, clock source B can be utilized as a
precise counter for time counting, e.g., the 2Hz clock can be
used for real time counting.
6.9.1 IO PWM
There is one IO PWM available and its duty is selectable from
1/256 to 254/256. The following figure is an example with
3/256-duration cycle. The PWMO waveform is made by
selecting a pulse width through Port_PWM_Ctrl. As a result,
each 256 cycles will generate a pulse width defined in control
port. These PWM signals can be applied for controlling the
speed of motor or other devices.
12 345 6 789
251 252 253 254 255 256 1
2
345
Tduty
...
Tp.w..mo
...
6.9.2 Timebase
Timebase, generated by 32768Hz crystal oscillator, is a
combination of frequency selection. Furthermore, timebase
generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt
sources (FIQ6/IRQ6, FIQ7/IRQ7) for Real-Time Clock
6.10 Sleep Mode, Wakeup, Halt Mode, and Watchdog
6.10.1 Sleep and wakeup modes
1) Sleep: After power-on reset, IC starts running until a sleep
command is issued. When a sleep command is
accepted, IC will turn the system clock (PLL) off.
After all, it enters sleep mode.
2) Wakeup: CPU awaking from sleep mode requires a wakeup
signal to turn the system clock (PLL) on. The
FIQ/IRQ signal makes CPU to complete the
wakeup process and initialization. The CPU
wakeup source is given in the following table.
Wakeup Source
FIQ source
Timer A interrupt
Timer B interrupt
Timer C interrupt
SPI interrupt
EXT1/EXT2/KEY
RTC
6.10.2 Watchdog Reset
The GPCE2P064A provides another important feature, watchdog
reset. If the watchdog function is enabled, a reset signal is
generated to reset system when watchdog counter is overflow.
The purpose of watchdog is to monitor whether the system
operates normally. Within a certain period, watchdog register
must be cleared. If it is not cleared, CPU assumes the program
has been running in an abnormal condition. As a result, the
CPU will reset the system to the initial state and start running the
program all over again.
© Generalplus Technology Inc.
Proprietary & Confidential
11
Jun 02, 2016
Version: 1.4
11 Page | ||
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| PDF Descargar | [ Datasheet GPCE2P064A.PDF ] | |
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