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Número de pieza | MB9BF106NA | |
Descripción | Microcontroller | |
Fabricantes | Spansion | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de MB9BF106NA (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! MB9B100A Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF102NA/RA, MB9BF104NA/RA, MB9BF105NA/RA,
MB9BF106NA/RA
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9B100A-DS706-00020 Revision 2.0 Issue Date December 15, 2014
1 page DataSheet
Multi-function Serial Interface (Max. 8channels)
・4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
・Operation mode is selectable from the followings for each channel.
・ UART
・ CSIO
・ LIN
・ I2C
[UART]
・Full-duplex double buffer
・Selection with or without parity supported
・Built-in dedicated baud rate generator
・External clock available as a serial clock
・Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
・Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
・Full-duplex double buffer
・Built-in dedicated baud rate generator
・Overrun error detect function available
[LIN]
・LIN protocol Rev.2.1 supported
・Full-duplex double buffer
・Master/Slave mode supported
・LIN break field generate (can be changed 13-16bit length)
・LIN break delimiter generate (can be changed 1-4bit length)
・Various error detect functions available (parity errors, framing errors, and overrun errors)
[I2C]
・Standard-mode (Max.100kbps) / Fast-mode (Max.400Kbps) supported
External Bus Interface
・Supports SRAM, NOR& NAND Flash device
・Up to 8 chip selects
・8/16-bit Data width
・Up to 25-bit Address bit
・Maximum area size : Up to 256 Mbytes
DMA Controller (8channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
・8 independently configured and operated channels
・Transfer can be started by software or request from the built-in peripherals
・Transfer address area: 32bit(4Gbyte)
・Transfer mode: Block transfer/Burst transfer/Demand transfer
・Transfer data type: byte/half-word/word
・Transfer block count: 1 to 16
・Number of transfers: 1 to 65536
December 15, 2014, MB9B100A-DS706-00020-2v0-E
3
5 Page PIN ASSIGNMENT
FPT-100P-M23
DataSheet
(TOP VIEW)
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
December 15, 2014, MB9B100A-DS706-00020-2v0-E
9
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet MB9BF106NA.PDF ] |
Número de pieza | Descripción | Fabricantes |
MB9BF106N | 32-bit Microcontroller | Fujitsu |
MB9BF106NA | Microcontroller | Spansion |
MB9BF106NA | 32-bit ARM Cortex-M3 based Microcontroller | Fujitsu |
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