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PDF MB9A310A Data sheet ( Hoja de datos )
| Número de pieza | MB9A310A | |
| Descripción | Microcontroller | |
| Fabricantes | Spansion | |
| Logotipo |  |
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MB9A310A Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF311LA/MA/NA, MB9AF312LA/MA/NA,
MB9AF314LA/MA/NA, MB9AF315MA/NA, MB9AF316MA/NA
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9A310A-DS706-00012 Revision 3.0 Issue Date December 26, 2014
1 page  
DataSheet
Multi-function Serial Interface (Max 8channels)
4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
Operation mode is selectable from the followings for each channel.
UART
CSIO
LIN
I2C
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)*
Various error detection functions available (parity errors, framing errors, and overrun errors)
* : MB9AF311LA, F312LA and F314LA do not support Hardware Flow control
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed 13-16bit length)
LIN break delimiter generation (can be changed 1-4bit length)
Various error detection functions available (parity errors, framing errors, and overrun errors)
[I2C]
Standard-mode (Max 100kbps) / Fast-mode (Max 400Kbps) supported
External Bus Interface*
Supports SRAM, NOR Flash device
Up to 8 chip selects
8/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
* : MB9AF311LA, F312LA and F314LA do not support External Bus Interface
DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32bit(4Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
December 16, 2014, MB9A310A-DS706-00012-3v0-E
3
5 Page 
DataSheet
PACKAGES
Package
Product name
MB9AF311LA
MB9AF312LA
MB9AF314LA
LQFP:FPT-64P-M38 (0.5mm pitch)
LQFP:FPT-64P-M39 (0.65mm pitch)
QFN:LCC-64P-M24 (0.5mm pitch)
LQFP:FPT-80P-M37 (0.5mm pitch)
LQFP:FPT-100P-M23 (0.5mm pitch)
QFP:FPT-100P-M06 (0.65mm pitch)
BGA:BGA-112P-M04 (0.8mm pitch)
-
-
-
-
MB9AF311MA
MB9AF312MA
MB9AF314MA
MB9AF315MA
MB9AF316MA
-
-
-
-
-
-
MB9AF311NA
MB9AF312NA
MB9AF314NA
MB9AF315NA
MB9AF316NA
-
-
-
-
*
: Supported
* : MB9AF315NA, MB9AF316NA are planning
Note: Refer to "PACKAGE DIMENSIONS" for detailed information on each package.
December 16, 2014, MB9A310A-DS706-00012-3v0-E
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB9A310A.PDF ] | |
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