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PDF CPC7591 Data sheet ( Hoja de datos )
| Número de pieza | CPC7591 | |
| Descripción | Line Card Access Switch | |
| Fabricantes | IXYS | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CPC7591 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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INTEGRATED CIRCUITS DIVISION
CPC7591
Line Card Access Switch
Features
• TTL Logic Level Inputs for 3.3V Logic Interfaces
• Smart Logic for Power Up / Hot Plug State Control
• Improved Switch dV/dt Immunity of 500 V/s
• Monolithic IC Reliability
• Low, Matched RON
• Eliminates the Need for Zero-Cross Switching
• Flexible Switch Timing for Transition from Ringing
Mode to Idle/Talk Mode.
• Clean, Bounce-Free Switching
• Tertiary Protection Consisting of Integrated Current
Limiting, Voltage Clamping, and Thermal Shutdown
for SLIC Protection
• 5V Operation with Power Consumption < 10 mW
• Intelligent Battery Monitor
• Latched Logic-Level Inputs, no External Drive
Circuitry
• Small 16-pin SOIC
Applications
• VoIP Gateways
• Central office (CO)
• Digital Loop Carrier (DLC)
• PBX Systems
• Digitally Added Main Line (DAML)
• Hybrid Fiber Coax (HFC)
• Fiber in the Loop (FITL)
• Pair Gain System
• Channel Banks
Description
The CPC7591 is a member of IXYS Integrated
Circuits Division’s next generation Line Card Access
Switch (LCAS) family. This monolithic 4-pole solid
state switch is available in a 16-pin SOIC package. It
provides the necessary functions to replace the
2-Form-C electromechanical ringing relay and it’s
associated snubber circuitry on traditional analog line
cards or contemporary integrated voice and data (IVD)
line cards found in Central Office (CO), Access, and
PBX equipment. Because this device contains solid
state switches for tip and ring line break and for ringing
injection/return, it requires only a +5 V supply for
operation and TTL logic-level inputs for control. The
CPC7591 provides stable start-up conditioning during
system power up and for hot plug insertion
applications. Once active, the inputs respond to
traditional TTL logic levels, enabling the CPC7591 to
be used with 3.3V-only logic.
For negative transient voltage protection the
CPC7591BA version includes SCRs to provide
voltage fold-back protection for the SLIC and
subsequent circuitry, while the CPC7591BB version
utilizes clamping diodes to the VBAT pin. For positive
transient voltage protection all versions provide
clamping diodes to the FGND pin.
Ordering Information
Pb e3
Part #
Description
CPC7591BA
CPC7591BATR
CPC7591BB
CPC7591BBTR
16-Pin SOIC, with Protection SCR, 50/Tube
16-Pin SOIC, with Protection SCR, 1000/Reel
16-Pin SOIC, without Protection SCR, 50/Tube
16-Pin SOIC, without Protection SCR, 1000/Reel
Figure 1. CPC7591 Block Diagram
+5 Vdc
Tip
Ring
T 3LINE
Secondary
Protection
RLINE 14
6 TRINGING
SW3
X
X
SW1
SW2
X
X
SW4
VBAT
12 RRINGING
300Ω
(min.)
RINGING
CPC7591
7 VDD
2 TBAT
Switch
VREF Control
Logic
1 SCR Trip Circuit
FGND (CPC7591BA)
16
VBAT
98
DGND
15 RBAT
L
A 10
T
C 11
H
DS-CPC7591-R06
www.ixysic.com
SLIC
INRINGING
LATCH
TSD
1
1 page  
INTEGRATED CIRCUITS DIVISION
CPC7591
1.6 Switch Specifications
1.6.1 Break Switches, SW1 and SW2
Parameter
Off-State
Leakage Current
On Resistance
On Resistance
Matching
DC current limit
Dynamic current limit
(t 0.5 s)
Logic input to switch
output isolation
dV/dt sensitivity
Test Conditions
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
+25 C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
+85 C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
-40 C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
ISW(on) = ±10 mA, ±40 mA,
RBAT and TBAT = -2 V
+25 C
+85 C
-40 C
Per SW1 & SW2 On Resistance test
conditions.
VSW(on) = ±10V
+25 C
+85 C
-40 C
Break switches on, all other switches
off. Apply ±1 kV 10x1000 s pulse with
appropriate protection in place.
Logic Inputs = GND
+25 C, VSW (TLINE, RLINE) = ±320 V
+85 C, VSW (TLINE, RLINE) = ±330 V
-40 C, VSW (TLINE, RLINE) = ±310 V
100VPP Square Wave, 100Hz
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
Symbol
ISW
RON
RON
ISW
ISW
ISW
-
Minimum
-
-
-
-
80
-
-
-
-
-
-
Typical
0.1
0.3
0.1
14.5
20.5
10.5
0.15
300
160
400
2.5
0.1
0.3
0.1
500
Maximum
1
-
28
-
0.8
-
425
-
1
-
Unit
A
mA
A
A
V/s
R06 www.ixysic.com
5
5 Page 
INTEGRATED CIRCUITS DIVISION
CPC7591
To facilitate hot plug insertion and system power up
state control, the LATCH pin has an integrated weak
pull up resistor to the VDD power rail that will hold a
non-driven LATCH pin at a logic high state. This
enables board designers to use the CPC7591 with
FPGAs and other devices that provide high
impedance outputs during power up and logic
configuration. The weak pull up allows a fan out of up
to 32 when the system’s LATCH control driver has a
logic low minimum sink capability of 4mA.
2.2.2 Hot Plug and Power Up Circuit Design
Considerations
There are six possible start up scenarios that can
occur during power up. They are:
1. All inputs defined at power up & LATCH = 0
2. All inputs defined at power up & LATCH = 1
3. All inputs defined at power up & LATCH = Z
4. All inputs not defined at power up & LATCH = 0
5. All inputs not defined at power up & LATCH = 1
6. All inputs not defined at power up & LATCH = Z
Under all of the start up situations listed above the
CPC7591 will hold all of it’s switches in the all-off state
during power up. When VDD requirements have been
satisfied the LCAS will complete it’s start up procedure
in one of three conditions.
For start up scenario 1 the CPC7591 will transition
from the all-off state to the state defined by the inputs
when VDD is valid.
For start up scenarios 2, 3, 5, and 6 the CPC7591 will
power up in the all-off state and remain there until the
LATCH pin is pulled low. This allows for an indefinite
all-off state for boards inserted into a powered system
but are not configured for service or boards that need
to wait for other devices to be configured first.
Start up scenario 4 will start up with all switches in the
all-off state but upon the acceptance of a valid VDD the
LCAS will revert to either the talk state or the ringing
state and there after may randomly change states
based on input pin leakage currents and loading.
Because the LCAS state after power up can not be
predicted with this start up condition it should never be
utilized.
On designs that do not wish to individually control the
LATCH pins of multiple-port cards it is possible to bus
many (or all) of the LATCH pins together to create a
single board level input enable control.
2.3 Switch Logic
2.3.1 Start-up
The CPC7591 uses smart logic to monitor the VDD
supply. Any time the VDD is below an internally set
threshold, the smart logic places the control logic to
the all-off state. An internal pullup on the LATCH pin
locks the CPC7591 in the all-off state following
start-up until the LATCH pin is pulled down to a logic
low. Prior to the assertion of a logic low at the LATCH
pin, the switch control inputs must be properly
conditioned.
2.3.2 Switch Timing
The CPC7591 provides, when switching from the
ringing state to the talk state, the ability to control the
release timing of the ringing switches SW3 and SW4
relative to the state of the break switches SW1 and
SW2 using simple TTL logic-level inputs. The two
available techniques are referred to as
make-before-break and break-before-make operation.
When the switch contacts of SW1 and SW2 are closed
(made) before the ringing switch contacts of SW3 and
SW4 are opened (broken), this is referred to as
make-before-break operation. Break-before-make
operation occurs when the ringing contacts of SW3
and SW4 are opened (broken) before the switch
contacts of SW1 and SW2 are closed (made). With
the CPC7591, make-before-break and
break-before-make operations can easily be
accomplished by applying the proper sequence of TTL
logic-level inputs to the device.
2.3.3 Make-Before-Break Operation
To use make-before-break operation, change the logic
inputs from the ringing state directly to the talk state.
Application of the talk state opens the ringing return
switch, SW3, as the break switches SW1 and SW2
close. The ringing switch, SW4, remains closed until
the next zero-crossing of the ringing current. While in
the make-before-break state, ringing potentials in
excess of the CPC7591 protection circuitry thresholds
will be diverted away from the SLIC. This operational
sequence is shown below in the “Make-Before-Break
Ringing to Talk Transition Logic Sequence” on page 12.
R06 www.ixysic.com
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CPC7591.PDF ] | |
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