|
|
PDF CPC5712 Data sheet ( Hoja de datos )
| Número de pieza | CPC5712 | |
| Descripción | Voltage Monitor | |
| Fabricantes | IXYS | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CPC5712 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
INTEGRATED CIRCUITS DIVISION
CPC5712
Voltage Monitor with Detectors
Features
• CPC5712 Outputs:
• Two Independent Programmable Level Detectors
with Programmable Hysteresis
• Fixed-Level Polarity Detector with Hysteresis
• Differential Linear Output
• Minimum External Components
• Excellent Common-Mode Rejection Ratio
(CMRR) > 55dB
• Application circuits meet isolation requirements of
worldwide telephony standards
• Worldwide telephone network compatibility
• Single Supply Operation, 3.0V to 5.5V
• High differential input impedance
• Very low common-mode input impedance
• Fixed Gain
• TTL Compatible CMOS Logic Level outputs
• Small SOP 16-Pin package
Applications
• VoIP Gateways, IP-PBX, xDSL
• TIP/RING Monitoring
• Line-In-Use Detection
• Polarity Detection for Caller ID, Enhanced 911
• Battery Detection, PSTN Check
• Non-telephony voltage level detection applications
• Instrumentation
• Industrial Controls
Pb e3
Description
The CPC5712 is a special purpose Voltage Monitor
with Detectors integrated circuit that is used in various
high-voltage telephony applications such as VoIP
gateways and IP-PBXs. The device monitors the
TIP/RING potential through a high-impedance divider
(resistor isolation) to derive two programmable signal
level detects, polarity information, and a scaled
representation of the phone line voltages. In use, the
resistor divider and the high input impedance of the
CPC5712 make the circuit practically undetectable on
the line.
The two voltage-level detects are programmed with
external resistors, which gives the designer complete
freedom with respect to line voltage detection levels.
The level settings also have programmable hysteresis
to prevent false triggering conditions. Detection of
these levels allows the user to determine the condition
of the line.
This device can also be used in non-telephony
applications such as instrumentation and industrial
controls, especially when a low-level differential level
needs to be detected in the presence of a large
common-mode voltage.
Ordering Information
Part
CPC5712U
CPC5712UTR
Description
16-Pin SOP (100/Tube)
16-Pin SOP (2000/Reel)
CPC5712 With Support Components
V+
1
VCC
CPC5712
TIP
RING
RIN1
RDIFF
R
IN2
7 IN+ +
-8 IN-
G=5
GND
VREF
OUT+ 5
OUT - 6
OUT+
POLARITY 4
DET1 3
VL1 VH1 VL2 VH2
DET2 2
16 15 14 9
10 11 12 13
+ Analog Output
- Analog Output
Polarity Output
Voltage Level Detect 1
Voltage Level Detect 2
R1 R2 R3 R4 R5
DS-CPC5712-R02
www.ixysic.com
1
1 page  
INTEGRATED CIRCUITS DIVISION
CPC5712
2. Functional Description
2.1 Overview
Clare’s CPC5712 is a generalized building block IC for
telephone systems that is connected, through a
resistor network, to the TIP and RING leads. From the
TIP and RING line voltage, the CPC5712 provides a
buffered and amplified differential linear representation
output voltage, a polarity detect signal, and two
programmable level detect signals. From these
detected levels, certain line conditions can be inferred
such as Line-In-Use and battery presence. The
CPC5712 provides TTL/CMOS compatible outputs for
the polarity and programmable level detectors.
The polarity detect and the two programmable level
detects all incorporate hysteresis to provide noise
immunity and eliminate rapid output state changes in
the presence of large voice signals. Hysteresis
settings for the two programmable level detects are
independently programmable; however, the polarity
hysteresis is internally fixed.
The high and low thresholds of the two programmable
level detectors are set with external resistors, the
selection of which is described below.
Positive polarity, POLARITY = HIGH, is indicated for
an OUT+ level greater than the OUT- level while
negative polarity is indicated for an OUT+ level less
than OUT-. For a logic-high polarity detect output with
a normal battery feed of TIP more positive than RING,
the amplifier IN+ will need to be connected to the TIP
lead via the high impedance input resistors. Detection
and hysteresis thresholds for polarity are internal to
the device.
The CPC5712 is connected to the TIP/RING interface
through a high-impedance resistor divider to attenuate
the signal. The resistors in the divider network
become a distributed resistive isolation barrier
between the high-voltage line side and the low voltage
side. The attenuator and the CPC5712 present a high
impedance to TIP and RING, making the circuit almost
undetectable when used as a monitoring device.
2.2 Line Side Interface
IN+, IN-: Analog inputs. The differential signal across
these inputs is amplified and brought out to the pins
OUT+ and OUT-. A nominal reference voltage bias of
1.5V is applied to IN+ and IN- by circuitry internal to
the chip. Because the voltage across TIP and RING
can be very large, TIP and RING cannot be directly
connected to IN+ and IN-. A resistor divider network
defined by RIN1, RIN2 and RDIFF attenuates the high
voltage signal across TIP and RING (see ). The
resulting low voltage differential signal across RDIFF is
applied to the inputs IN+ and IN-. Resistors RIN1, RIN2
and RDIFF are external resistors that must be supplied
by the user.
Any component sizing and value recommendations
given in the circuits described in this document will
need to be reviewed with regard to the regulatory and
safety requirements for each particular application. For
example, the resistors selected for RIN1 and RIN2,
shown in , are recommended to be a pair of 1206
surface mount size resistors in series to provide for
high-voltage isolation.
2.3 Monitor Output
OUT+, OUT-: Analog outputs. The differential signal
across these outputs is the same as the differential
input signal, except there has been a differential gain
of 5 applied to it. A nominal reference voltage bias of
1.5V is applied to OUT+ and OUT- by circuitry internal
to the chip.
2.4 Detector Outputs
DET2, DET1, POLARITY: Digital outputs. These
signals show whether threshold 2 has been crossed,
threshold 1 has been crossed, and the polarity of the
TIP to RING potential.
When configured as shown in , POLARITY will be high
after the TIP to RING potential (TIP more positive than
RING) has increased to a nominal 2V. POLARITY will
switch low after the TIP to RING voltage decreases to
approximately -2V. For example, if the TIP to RING
voltage starts at -48V, POLARITY will be low. As the
TIP to RING voltage increases to +1V, POLARITY will
remain low. As the TIP to RING voltage increases
beyond it’s internally set positive threshold, the
POLARITY output will switch high. POLARITY will
remain high until the TIP to RING voltage decreases
below it’s internally set negative threshold. Because
these polarity thresholds are set internally they are not
user adjustable.
R02 www.ixysic.com
5
5 Page 
INTEGRATED CIRCUITS DIVISION
4.5 CPC5712U 16-Pin SOP Package
4.902 ± 0.102
(0.193 ± 0.004)
0.254 MAX - 0.178 MIN
(0.010 MAX - 0.007 MIN)
3.812 ± 0.076
(0.150 ± 0.003)
6.045 ± 0.153
(0.238 ± 0.006)
0.712 ± 0.051
(0.028 ± 0.002)
Pin 1
0.635
(0.025)
0.254 ± 0.051
(0.010 ± 0.002)
0.051 MIN, 0.305 MAX
(0.002 MIN, 0.012 MAX)
1.447 ± 0.076
(0.057 ± 0.003)
0.762 MAX - 0.508 MIN
(0.030 MAX - 0.020 MIN)
1.829 MAX
(0.072 MAX)
CPC5712
PCB Land Pattern
5.40
(0.213)
1.55
(0.061)
0.635
(0.025)
0.40
(0.0157)
Dimensions
mm
(inches)
4.6 CPC5712UTR Tape and Reel Packaging
330.2 DIA.
(13.00 DIA.)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
B0=5.30
(0.209)
W=12.00
(0.472)
Embossed Carrier
K0= 2.10
(0.083)
A0=6.50
(0.256)
P=8.00
(0.315)
User Direction of Feed
Dimensions
mm
(inches)
Embossment
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specification: DS-CPC5712-R02
© Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/22/2012
R02 www.ixysic.com
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CPC5712.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CPC5710N | Phone Line Monitor (PLM) IC | IXYS |
| CPC5710N | Phone Line Monitor (PLM) IC |  Clare |
| CPC5712 | Voltage Monitor | IXYS |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |