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PDF ALT6725 Data sheet ( Hoja de datos )

Número de pieza ALT6725
Descripción Dual-band Cellular & PCS LTE 3.4V Linear Power Amplifier Module
Fabricantes ANADIGICS 
Logotipo ANADIGICS Logotipo



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No Preview Available ! ALT6725 Hoja de datos, Descripción, Manual

FEATURES
• InGaP HBT Technology
• High Efficiency:
35 % @ POUT = +27.5 dBm
16 % @ POUT = +15 dBm
8 % @ POUT = +9 dBm
• Low Quiescent Current: 4 mA
• Internal Voltage Regulation
• Built-in Directional Coupler
• Common VMODE Control Line
• Suitable for SMPS and average power tracking
systems with variable supply voltages
• APT can reduce TS.09 average power
consumption more than 25%
• Reduced External Component Count
• Thin Package: 0.9 mm
• RoHS Compliant Package, 260 oC MSL-3
ALT6725
HELP3ETM Dual-band Cellular & PCS LTE
3.4 V Linear Power Amplifier Module
PRELIMINARY DATA SHEET - Rev 1.0
is designed for use both with and without average
power tracking (APT). APT can be used to optimize
the Vcc level for the desired output power level and
linearity, which greatly reduces the total current
drawn from the battery. This feature, in conjunction
with selectable operating modes, enables significant
improvements in overall power added efficiency of the
ALT6725 across the entire dynamic range of operating
powers. APT requires use of an external variable
voltage supply (DC-DC converter), which is used to
provide the variable voltage to Vcc pad of the amplifier.
A low-leakage shutdown mode increases standby
time. This PA has built-in directional couplers for each
band, with a common coupler output port CPL_OUT.
The 3 mm x 5 mm x 0.9 mm surface mount package
incorporates matching networks optimized for output
power, efficiency and linearity in a 50 Ω system. The
device is manufactured on an advanced InGaP HBT
MMIC technology offering state-of-the-art reliability,
temperature stability, and ruggedness.
APPLICATIONS
• Dual-band Wireless Handsets and Data Devices
for LTE/CDMA/EVDO networks:
• UMTS Band 5, 6, 18, 19, & 26
• UMTS Band 2 & 25
• Cellular BC 0 and 10
• PCS BC 1 and 14
VEN_CELL 1
RFIN_CELL 2
Bias Control
Voltage Regulation
CPL
14 GND
13 RFOUT_CELL
PRODUCT DESCRIPTION
ALT6725 addresses the demand for increased
integration in dual-band handsets for LTE networks.
The small footprint 3 mm x 5 mm x 0.9 mm surface
mount RoHS compliant package contains independent
RF PA paths to ensure optimal performance in both
frequency bands in less board area than two single
band PAs. The package pinout was chosen to enable
handset manufacturers to independently provide
bias to both power amplifiers and simplify control
with common mode pins. The ALT6725 is part of
ANADIGICS’ 3rd generation of High-Efficiency-at-
Low-Power (HELP3E™) family of power amplifiers,
which deliver low quiescent currents and significantly
greater efficiency through selectable bias modes for
high, medium and low power operation. The ALT6725
VMODE1 3
VBATT 4
VMODE2 5
RFIN_PCS 6
VEN_PCS 7
07/2012
12 VCC
11 VCCA
10 CPLOUT
CPL 9 GND
Bias Control
Voltage Regulation
8 RFOUT_PCS
GND at Slug (pad)
Figure 1: Block Diagram

1 page




ALT6725 pdf
ALT6725
Table 5: Electrical Specifications - Cellular Band (BC 0, 10)
(TC = +25 °C, VBATT = VCC = +3.4 V, VEN_CELL = +1.8 V, 50 system, CDMA2000 RC-1 waveform)
PARAMETER
COMMENTS
MIN TYP MAX UNIT
POUT
VMODE1
VMODE2
- 28 -
+28 dBm 0 V
0V
Gain
- 17 -
dB +16 dBm 1.8 V
0V
- 12 -
+10 dBm 1.8 V
1.8 V
Adjacent Channel Power
at ± 1.25 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
- -48.5
- -52
- -53.5
-
-
-
+28 dBm
dBc +16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
Adjacent Channel Power
at ± 1.98 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
- -58
-
+28 dBm 0 V
- -59 - dBc +16 dBm 1.8 V
- -68
-
+10 dBm 1.8 V
0V
0V
1.8 V
- 37.5 -
+28 dBm 0 V
0V
(1)
- 19.5 -
% +16 dBm 1.8 V
0V
- 10 -
+10 dBm 1.8 V
1.8 V
Quiescent Current (Icq)
- 4 - mA through VCC pins, VMODE1,2 = +1.8 V
Mode Control Current
- 0.5 -
mA through VMODE pin, VMODE1,2 = +1.8 V
BATT Current
- 1.5 -
mA through VBATT pin, VMODE1,2 = +1.8V
Enable Current
- 0.3 -
mA through VEN_CELL pin, VMODE1,2 = +1.8 V
Total Decoder Current on
VBATT (in Shutdown mode)
-
7
-
µA
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
HBT Leakage Current (VCC)
(Shutdown mode)
- <1 -
µA
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
Noise In Receive Band
- -133 - dBm/Hz 869 MHz to 894 MHz
Harmonics
2fO
3fO, 4fO
-
-
-
-
-35
-35
dBc POUT < +28 dBm
Input Impedence
- 2:5:1 - VSWR
Coupling Factor
- 22 -
dB
Spurious Output Level
(all spurious outputs)
POUT < +28 dBm
-
-
-65
dBc
In-band load VSWR < 5:1
Out-of-band load VSWR < 10:1
Applies over all operating conditions
Load mismatch stress with no
permanent degradation or failure
8:1 -
- VSWR Applies over full operating range
Notes:
(1) PAE and ACP measured at 836.5 MHz.
5
PRELIMINARY DATA SHEET - Rev 1.0
07/2012

5 Page





ALT6725 arduino
ALT6725
PCB BOARD Design GuidELINES
Refer to Figure 7 for the recommended PCB metal
design, soldermask design, and stencil print patterns
when assembling with ANADIGICS modules [5].
It is important to note that the PCB metal design is
dependent upon several factors: the electrical and
thermal performance requirements of the product,
and the PCB-to-device interconnect pattern. The
PCB metal design recommendations primarily deal
with te PCB-to-device interconnection. Specific
board-level electrical and thermal performance re-
quirements will be dictated by the physical geometry
of the specific application and are the responsibility
of the end product manufacturer.
Figure 7: PCB Board Design Guidelines
11
PRELIMINARY DATA SHEET - Rev 1.0
07/2012

11 Page







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