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PDF PI6ULS5V9517A Data sheet ( Hoja de datos )
| Número de pieza | PI6ULS5V9517A | |
| Descripción | Level Translating I2C Bus/SMBus Repeater | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6ULS5V9517A
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Level Translating I2C Bus/SMBus Repeater
Features
2 channel, bidirectional buffer
I2C-bus and SMBus compatible
Port A operating supply voltage range of 0.8 V to
5.5 V
Port B operating supply voltage range of 2.2 V to
5.5 V
Voltage level translation from 0.8 V to 5.5 V and
from 2.2 V to 5.5 V
Active HIGH repeater enable input
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the
repeater
Accommodates Standard-mode and Fast-mode I2C-
bus devices and multiple masters
Powered-off high-impedance I2C-bus pins
5.5 V tolerant I2C-bus and enable pins
0 Hz to 400 kHz clock frequency (the maximum
system operating frequency may be less than 400
kHz because of the delays added by the repeater)
ESD protection exceeds 8KV HBM per JESD22-
A114
Package: MSOP-8L, SOIC-8L and DFN2x3-8L
Description
The PI6ULS5V9517A is a CMOS integrated circuit
intended for I2C-bus or SMBus applications. It can
provide level shifting between low voltage (down to 0.8
V) and higher voltage (2.2V to 5.5V) in mixed-mode
applications. And it enables I2C and similar bus system
to be extended, without degeradation of peformance
even during level shifting.
The PI6ULS5V9517A enables the system designer to
isolate two halves of a bus for both voltage and
capacitance, accommodating more I2C devices or longer
trace length. It also permits extension of the I2C-bus by
providing bidirectional buffering for both the data (SDA)
and the clock (SCL) lines, thus allowing two buses of
400 pF to be connected in an I2C application.
Pin Description
Pin No
MSOP-8
SOIC-8
DFN2x3-8L
17
28
31
42
53
64
75
86
Name
VCC(A)
SCLA
SDAA
GND
EN
SDAB
SCLB
VCC(B)
Description
port A supply voltage
(0.8 to 5.5 V)
serial clock port A bus
serial data port A bus
supply ground (0 V)
active HIGH repeater
enable input
serial data port B bus
serial clock port B bus
port B supply voltage
(2.2 to 5.5 V)
Pin Configuration
MSOP-8 and SOIC-8
DFN2x3-8L(Top view)
2015-10-0003
PT0459-7 10/20/15
1
1 page  
PI6ULS5V9517A
Level Translating I2C-Bus/SMBus Repeater
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Functional Description
The PI6ULS5V9517A is a CMOS integrated circuit intended for I2C-bus or SMBus applications. It can provide
level shifting between low voltage (down to 0.8 V) and higher voltage (2.2 V to 5.5 V) in mixed-mode applications.
And it enables I2C and similar bus system to be extended, without degradation of performance even during level
shifting.
The PI6ULS5V9517A enables the system designer to isolate two halves of a bus for both voltage and capacitance,
accommodating more I2C devices or longer trace length. It also permits extension of the I2C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus allowing two buses of 400 pF to be
connected in an I2C application.
The B-side drivers operate from 2.2 V to 5.5 V. The output low level of port B internal buffer is approximately 0.5
V, while the input voltage must be 70mV lower (0.43V) or even more lower. The nearly 0.5V low signal is called a
buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This
feature prevents a lockup condition from occurring when the input low condition is released. This type of design on B
port prevents it from being used in series with another PI6ULS5V9517A (B side) or similar devices ,because they
don’t recognize buffer low signals as a valid low .
The A-side drivers operate from 0.8 V to 5.5 V. The output low level of port A internal buffer is nearly 0V,while
the input low level is set at 0.3Vcc(A) to accommodate the need for a lower LOW level in systems where the low
voltage side supply voltage is as low as 0.8 V. Port A of two or more PI6ULS5V9517As can be connected together to
allow a star topography with port A on the common bus. And port A can be connected directly to any other buffer with
static or dynamic offset voltage. Multiple PI6ULS5V9517As can be connected in series, port A to port B, with no
build-up in offset voltage with only time off light delays to consider.
The EN pin can also be used to turn the drivers on and off. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an I2C-bus operation because
disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C-
bus parts being enabled. The enable pin should only change state when the global bus and the repeater port are in an
idle state to prevent system failures.
After power-up and with the EN HIGH, a LOW level on port A (below 0.3Vcc(A)) turns the corresponding port B
driver (either SDA or SCL) on and drives port B down to about 0.5 V. When port A rises above 0.3Vcc(A), the port B
pull-down driver is turned off and the external pull-up resistor pulls the pin HIGH. When port B falls first and goes
below 0.3Vcc(B) the port A driver is turned on and port A pulls down to 0 V. The port B pull-down is not enabled
unless the port B voltage goes below 0.4 V. If the port B low voltage does not go below 0.5 V, the port A driver will
turn off when port B voltage is above 0.7Vcc(B). If the port B low voltage goes below 0.4 V, the port B pull-down
driver is enabled and port B will only be able to rise to 0.5 V until port A rises above 0.3Vcc(A). Then port B will
continue to rise being pulled up by the external pull-up resistor. The Vcc(A) is only used to provide the 0.3Vcc(A)
reference to the port A input comparators and for the power good detect circuit. The PI6ULS5V9517A logic and all
I/Os are powered by the Vcc(B) pin.
The EN pin is active high and allows the user to select when the repeater is active.This can be used to isolate a
badly behaved slave on power-up until after the system power-up reset. It should never change state during an I2C-bus
operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could
confuse the I2C-bus parts being enabled. The enable pin should only change state when the global bus and the repeater
port are in an idle state to prevent system failures.
As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered bus.
The PI6ULS5V9517A has standard open-collector configuration of the I2C bus. The size of these pullup resistors
depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with
Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3
mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Under certain conditions,
higher termination currents can be used.
2015-10-0003
PT0459-7 10/20/15
5
5 Page 
PI6ULS5V9517A
Level Translating I2C-Bus/SMBus Repeater
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Recommended Land pattern for TDFN2*3-8L
Note:
All linear dimensions are in millimeters
2015-10-0003
PT0459-7 10/20/15
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet PI6ULS5V9517A.PDF ] | |
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