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PDF COP425C Data sheet ( Hoja de datos )
| Número de pieza | COP425C | |
| Descripción | Single-Chip 1k and 2k CMOS Microcontrollers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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April 1992
COP424C COP425C COP426C COP324C COP325C
COP326C and COP444C COP445C COP344C COP345C
Single-Chip 1k and 2k CMOS Microcontrollers
General Description
The COP424C COP425C COP426C COP444C and
COP445C fully static Single-Chip CMOS Microcontrollers
are members of the COPSTM family fabricated using dou-
ble-poly silicon gate microCMOS technology These Con-
troller Oriented Processors are complete microcomputers
containing all system timing internal logic ROM RAM and
I O necessary to implement dedicated control functions in a
variety of applications Features include single supply oper-
ation a variety of output configuration options with an in-
struction set internal architecture and I O scheme de-
signed to facilitate keyboard input display output and BCD
data manipulation The COP424C and COP444C are 28 pin
chips The COP425C and COP445C are 24-pin versions (4
inputs removed) and COP426C is 20-pin version with 15 I O
lines Standard test procedures and reliable high-density
techniques provide the medium to large volume customers
with a customized microcontroller at a low end-product cost
These microcontrollers are appropriate choices in many de-
manding control environments especially those with human
interface
The COP424C is an improved product which replaces the
COP420C
COPSTM MicrobusTM and MICROWIRETM are trademarks of National Semiconductor Corp
TRI-STATE is a registered trademark of National Semiconductor Corp
Features
Y Lowest power dissipation (50 mW typical)
Y Fully static (can turn off the clock)
Y Power saving IDLE state and HALT mode
Y 4 ms instruction time plus software selectable clocks
Y 2k x 8 ROM 128 x 4 RAM (COP444C COP445C)
Y 1k x 8 ROM 64 x 4 RAM (COP424C COP425C
COP426C)
Y 23 I O lines (COP444C and COP424C)
Y True vectored interrupt plus restart
Y Three-level subroutine stack
Y Single supply operation (2 4V to 5 5V)
Y Programmable read write 8-bit timer event counter
Y Internal binary counter register with MICROWIRETM
serial I O capability
Y General purpose and TRI-STATE outputs
Y LSTTL CMOS output compatible
Y MicrobusTM compatible
Y Software hardware compatible with COP400 family
Y Extended temperature range devices COP324C
COP325C COP326C and COP344C COP345C (b40 C
to a85 C)
Y Military devices (b55 C to a125 C) to be available
Block Diagram
C1995 National Semiconductor Corporation TL DD 5259
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FIGURE 1
Not available on COP426C COP326C
TL DD 5259 – 1
RRD-B30M105 Printed in U S A
1 page  
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COP324C COP325C COP326C and COP344C COP345C
AC Electrical Characteristics b40 CsTAsa85 C unless otherwise specified
Parameter
Conditions
Min Max Units
Instruction Cycle Time (tc)
Operating CKI
Frequency
d4 mode
d8 mode
d16 mode
d4 mode
d8 mode
d16 mode
(
(
VCCt4 5V
4 5VlVCCt3 0V
VCCt4 5V
4 5VlVCCt3 0V
4 DC ms
16 DC ms
DC 1 0 MHz
DC 2 0 MHz
DC 4 0 MHz
DC 250 kHz
DC 500 kHz
DC 1 0 MHz
Duty Cycle (Note 4)
Rise Time (Note 4)
Fall Time (Note 4)
Instruction Cycle Time
RC Oscillator (Note 4)
f1e4 MHz
f1e4 MHz external clock
f1e4 MHz external clock
R e 30k g5% VCC e 5V
C e 82 pF g5% (d4 Mode)
40 60 %
60 ns
40 ns
5 11 ms
Inputs (See Figure 3 )
tSETUP
tHOLD
G Inputs
(SI Inputs
All Others
VCCt 4 5V
VCCt 4 5V
4 5VlVCCt3 0V
tc 4a 7
03
17
0 25
10
ms
ms
ms
ms
ms
Output Propagation Delay
tPD1 tPD0
tPD1 tPD0
VOUTe1 5V CLe100 pF RLe5k
VCCt 4 5V
4 5VlVCCt3 0V
1 0 ms
4 0 ms
Microbus Timing
Read Operation (Figure 4 )
Chip Select Stable before RD btCSR
Chip Select Hold Time for RD btRCS
RD Pulse WidthbtRR
Data Delay from RD btRD
RD to Data Floating btDF (Note 4)
CLe50 pF VCCe5Vg5%
65 ns
20 ns
400 ns
375 ns
250 ns
Write Operation (Figure 5 )
Chip Select Stable before WR btCSW
Chip Select Hold Time for WR btWCS
WR Pulse WidthbtWW
Data Set-Up Time for WR btDW
Data Hold Time for WR btWD
INTR Transition Time from WR btWI
65 ns
20 ns
400 ns
320 ns
100 ns
700 ns
Note 1 Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI CKO open and all other pins pulled up to VCC with 5k
resistors See current drain equation on page 17
Note 2 The HALT mode will stop CKI from oscillating in the RC and crystal configurations Test conditions all inputs tied to VCC L lines in TRI-STATE mode and
tied to ground all outputs low and tied to ground
Note 3 When forcing HALT current is only needed for a short time (approx 200 ns) to flip the HALT flip-flop
Note 4 This parameter is only sampled and not 100% tested Variation due to the device included
Note 5 Voltage change must be less than 0 5 volts in a 1 ms period
Note 6 SO output sink current must be limited to keep VOL less than 0 2VCC when part is running in order to prevent entering test mode
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5
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Functional Description (Continued)
The HALT mode is the minimum power dissipation state
Note If the user has selected dual-clock with D0 as external
oscillator (option 30e2) AND the COP444C 424C is
running with the D0 clock the HALT mode either
hardware or software will NOT be entered Thus
the user should switch to the CKI clock to HALT Al-
ternatively the user may stop the D0 clock to mini-
mize power
CKO PIN OPTIONS
a Two-pin oscillator (Crystal) See Figure 9A
In a crystal controlled oscillator system CKO is used as
an output to the crystal network The HALT mode may be
entered by program control (HALT instruction) which
forces CKO high thus inhibiting the crystal network The
circuit can be awakened only by forcing the RESET pin to
a logic ‘‘0’’ (restart)
b One-pin oscillator (RC or external) See Figure 9B
If a one-pin oscillator system is chosen two options are
available for CKO
CKO can be selected as the HALT I O port In that
case it is an I O flip-flop which is an indicator of the
HALT status An external signal can over-ride this pin
to start and stop the chip By forcing a high level to
CKO the chip will stop as soon as CKI is high and
CKO output will stay high to keep the chip stopped if
the external driver returns to high impedance state
By forcing a low level to CKO the chip will continue
and CKO will stay low
As another option CKO can be a general purpose in-
put read into bit 2 of A (accumulator) upon execution
of an INIL instruction
OSCILLATOR OPTIONS
There are four basic clock oscillator configurations available
as shown by Figure 8
a Crystal Controlled Oscillator CKI and CKO are connect-
ed to an external crystal The instruction cycle time equals
the crystal frequency optionally divided by 4 8 or 16
b External Oscillator The external frequency is optionally
divided by 4 8 or 16 to give the instruction cycle time
CKO is the HALT I O port or a general purpose input
c RC Controlled Oscillator CKI is configured as a single pin
RC controlled Schmitt trigger oscillator The instruction
cycle equals the oscillation frequency divided by 4 CKO
is the HALT I O port or a general purpose input
d Dual oscillator By selecting the dual clock option pin D0
is now a single pin oscillator input Two configurations are
available RC controlled Schmitt trigger oscillator or exter-
nal oscillator
The user may software select between the D0 oscillator
(in that case the instruction cycle time equals the D0
oscillation frequency divided by 4) by setting the D0 latch
high or the CKI (CKO) oscillator by resetting D0 latch low
Note that even in dual clock mode the counter if mask-
programmed as a time-base counter is always connect-
ed to the CKI oscillator
For example the user may connect up to a 1 MHz RC
circuit to D0 for faster processing and a 32 kHz watch
crystal to CKI and CKO for minimum current drain and
time keeping
Note CTMA instruction is not allowed when chip is running
from D0 clock
Figures 10A and 10B show the clock and timer diagrams
with and without Dual clock
COP445C AND COP425C 24-PIN PACKAGE OPTION
If the COP444C 424C is bonded in a 24-pin package it be-
comes the COP445C 425C illustrated in Figure 2 Connec-
tion diagrams Note that the COP445C 425C does not con-
tain the four general purpose IN inputs (IN3 – IN0) Use of
this option precludes of course use of the IN options in-
terrupt feature external event counter feature and the
Microbus option which uses IN1 – IN3 All other options are
available for the COP445C 425C
Note If user selects the 24-pin package options 9 10 19
and 20 must be selected as a ‘‘0’’ (load to VCC on the
IN inputs) See option list
COP426C 20-PIN PACKAGE OPTION
If the COP425C is bonded as 20-pin device it becomes the
COP426C Note that the COP426C contains all the
COP425C pins except D0 D1 G0 and G1
Block Diagram (Continued)
FIGURE 9A Halt Mode Two-Pin Oscillator
11
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| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet COP425C.PDF ] | |
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