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PDF CY62157DV20 Data sheet ( Hoja de datos )
| Número de pieza | CY62157DV20 | |
| Descripción | 8M (512K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62157DV20
MoBL2
Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V to 2.2V
• Pin compatible with CY62157CV18
• Ultra low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 10 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA
Functional Description[1]
The CY62157DV20 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
Logic Block Diagram
8M (512K x 16) Static RAM
deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2)
LOW or both BHE and BLE are HIGH. The input/output pins
(I/O0 through I/O15) are placed in a high-impedance state
when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable
2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH)
or during a write operation (Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A18). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18).
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O8 to I/O15. See the truth table at the
back of this data sheet for a complete description of read and
write modes.
DATA IN DRIVERS
A10
A9
A8
A7
A 6 512K x 16
A 5 RAM ARRAY
A 4 2048 x 256 x 16
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power - down
Circuit
BHE
WE CE2
OE CE1
BLE
BHE CE2
BLE CE1
Note:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05136 Rev. *B
Revised March 17, 2003
1 page  
Switching Characteristics (Over the Operating Range)[9]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE[11]
tHZBE
Write Cycle[13]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW or CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[10]
OE HIGH to High Z[10, 12]
CE1 LOW or CE2 HIGH to Low Z[10]
CE1 HIGH or CE2 LOW to High Z[10, 12]
CE1 LOW or CE2 HIGH to Power-up
CE1 HIGH or CE2 LOW to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z[10]
BLE/BHE HIGH to High Z[10, 12]
Write Cycle Time
CE1 LOW or CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[10, 12]
WE HIGH to Low Z[10]
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
CY62157DV20-55
Min.
Max.
55
55
10
55
25
5
20
10
20
0
55
55
5
20
55
45
45
0
0
45
45
25
0
20
10
ADDRESS
DAT A OUT
tOHA
PREVIOUS DATA VALID
tAA
tRC
CY62157DV20
MoBL2
CY62157DV20-70
Min.
Max.
70
70
10
70
35
5
25
10
25
0
70
70
5
25
70
60
60
0
0
50
60
30
0
25
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA VALID
Notes:
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t
11. If both byte enables are toggled together, this value is 10 ns.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
13. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL.
14. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH.
15. WE is HIGH for Read cycle.
Document #: 38-05136 Rev. *B
Page 5 of 10
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| PDF Descargar | [ Datasheet CY62157DV20.PDF ] | |
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