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PDF HMC6545 Data sheet ( Hoja de datos )
| Número de pieza | HMC6545 | |
| Descripción | 32 Gbps Dual Channel Advanced Linear Equalizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Supports data rates from dc up to 32 Gbps
Protocol and data rate agnostic
Low latency (<170 ps)
Integrated AGC with differential sensitivity of <50 mV
Up to 20 dB programmable multiple unit interval input
equalization
Extended chromatic and polarization mode dispersion
tolerance
Programmable differential output amplitude control of up to
600 mV
Single 3.3 V supply eliminating external regulators
Wide temperature range from −40°C to +95°C
5 mm × 5 mm, 32-lead LFCSP package
APPLICATIONS
40 Gbps/100 Gbps DQPSK direct detection receivers
Short and long reach CFP2 and QSFP+ modules
CEI-28G MR and CEI-25G LR 100 GE line cards
16 Gbps and 32 Gbps Fibre Channel
Infiniband 14 Gbps FDR and 28 Gbps EDR rates
Signal conditioning for backplane and line cards
Broadband test and measurement equipment
GENERAL DESCRIPTION
The HMC6545 is a low power, high performance, fully
programmable, dual-channel, asynchronous advanced linear
equalizer that operates at data rates of up to 32 Gbps. The
HMC6545 is protocol and data rate agnostic, and it can operate
on the transmit path to predistort a transmitted signal to invert
channel distortion or on the receiver path to equalize the
distorted and attenuated received signal. The HMC6545 is
effective in dealing with chromatic and polarization mode
dispersion and intersymbol interference (ISI) caused by a wide
variety of transmission media (backplane or fiber) and channel
lengths.
The HMC6545 consists of an automatic gain control (AGC);
dc offset correction circuitry; a 9-tap, 18 ps spaced feedforward
equalizer (FFE); a summing node; and a linear programmable
output driver. The input AGC linearly attenuates or amplifies
the distorted input signal to generate a constant voltage at the
32 Gbps Dual Channel
Advanced Linear Equalizer
HMC6545
FUNCTIONAL BLOCK DIAGRAM
GND 1
INP0 2
INN0 3
GND 4
GND 5
INP1 6
INN1 7
GND 8
HMC6545
AGC
T/2 T/2 T/2 T/2
LPF
AGC
LPF
c0 c1 c2 cn
Σ
SERIAL CONTROL
REGISTERS
T/2 T/2 T/2 T/2
d0 d1 d2 dn
Σ
Figure 1.
24 GND
23 OUTP0
22 OUTN0
21 GND
20 GND
19 OUTP1
18 OUTN1
17 GND
PACKAGE
BASE
GND
input of the FFE. The 9-tap FFE is programmed via 2-wire
interface to generate wide range frequency responses that are
precursor or postcursor in nature for compensating signal
impairments. After FFE tap coefficients are summed at the
summing node, the signal is received by a linear output driver.
DC offset correction circuitry is controlled either automatically
or manually via Forward Error Correction (FEC).
All high speed differential inputs and outputs of the HMC6545 are
current mode logic (CML) and terminated on chip with 50 Ω to
the positive supply, 3.3 V, and can be dc-coupled or ac-coupled.
The inputs and outputs of the HMC6545 can be operated either
differentially or single-ended. The low power, high performance,
and feature rich HMC6545 is packaged in a 5 mm × 5 mm,
32-lead LFCSP package. The device uses a single 3.3 V supply,
eliminating external regulators. The HMC6545 operates over a
−40°C to +95°C temperature range.
Rev. A
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VCC to GND
All Pins to GND
Operating Ambient Temperature Range
Differential Peak-to-Peak Input Voltage
Swing
Maximum Input Voltage at CML Inputs
Maximum Input Voltage at Digital Inputs
(SDA, SCL, REGSEL1, REGSEL0, RST)
Maximum Peak Reflow Temperature
Maximum Junction Temperature
Continuous Power Dissipation (TA = 85°C,
Derate 46.59 mW/°C Above 85°C)
Thermal Resistance (Junction to EPAD)
ESD Sensitivity, Human Body Model
(HBM)
Rating
−0.6 V to +3.6 V
−0.3 V to VCC + 0.3 V
−40°C to +95°C
1.6 V p-p
VCC + 0.6 V
VCC + 0.6 V
260°C
125°C
1.86 W
21.46°C/W
Class 1C
HMC6545
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 5 of 23
5 Page 
Data Sheet
HMC6545
THEORY OF OPERATION
The HMC6545 advanced linear equalizer has two symmetrical
channels, each containing an input AGC, a 9-tap delay chain
with each delay tap connected to a variable tap amplifier, a
summation node combining the outputs of the tap amplifiers,
and an output driver.
INPUT RECEIVER
AGC
The HMC6545 has an integrated AGC that linearly amplifies/
attenuates the input signal, generating a fixed voltage swing
level for further processing in the FFE delay line. An input AGC
is required both to supply a well defined voltage swing level to
the FFE delay line and to control the internal and external (output)
voltage swings because the signal path is linear. The AGC has a
sensitivity level of 40 mV p-p differential. The HMC6545 processes
the input signal linearly at up to a 600 mV p-p differential input
voltage level.
The AGC loop bandwidth and settling time can be changed
using an external capacitor connected to the CAGC0/GND
and CAGC1/GND nodes. An internal 2.5 pF capacitor at these
nodes sets the default AGC settling time to 0.5 µs. The evaluation
board includes 1 nF capacitors for both channels.
Internal and External Offset Correction Circuitry
The input receiver has two modes of offset correction that can
be configured by changing the offset settings register via the
2-wire interface: automatic offset correction and manual offset
correction (all registers in Table 5 are identical to each other).
Table 5. Offset Settings Registers
Register
Description
Register 0x0A Channel 0 Offset Settings, Array A register
Register 0x2A Channel 0 Offset Settings, Array B register
Register 0x4A Channel 1 Offset Settings, Array A register
Register 0x6A Channel 1 Offset Settings, Array B register
By default, the input receiver is configured in the automatic
offset correction mode, which can correct up to ±60 mV of
input referred dc offset at the worst case AGC gain (maximum
AGC gain with a minimum input signal level). The input
referred automatic offset correction range changes depending
on the AGC gain and increases up to ±180 mV for minimum
AGC gain with a maximum signal level at the input of the
receiver.
Automatic offset correction loop bandwidth is externally set by
a series RC network (for each channel, R1/C1 and R2/C2), and
it is recommended to keep the component values as shown in
the evaluation board schematic (see Figure 35).
For Channel 1, Array A, automatic offset correction loop can be
disabled by setting Register 0x4A, Bit 6 to 0, which enables the
manual offset correction (set Register 0x0A for Channel 0,
Array A; Register 0x2A for Channel 0, Array B; and Register 0x6A
for Channel 1, Array B; see Table 5). Manual offset correction
amount can be adjusted by configuring Register 0x4A, Bits[5:0],
where Register 0x4A, Bit 5 defines the sign and Bits[4:0] define
the magnitude of gain (see Table 48). Similar to automatic offset
correction mode, manual offset correction dynamic range changes
with the AGC gain with the total correction being ±60 mV for
maximum AGC gain, which corresponds to about 2 mV/step
(5-bit control) adjustment resolution for maximum AGC gain.
For minimum AGC gain, the correction dynamic range increases
to ±180 mV, and the minimum step for adjustment increases to
6 mV/step.
FFE DELAY LINE
The FFE delay line receives an input signal from the AGC (with
a controlled magnitude), and this signal propagates along a
delay line composed of eight delay elements, where each delay
element has 18 ps nominal propagation. The delayed signals are
then multiplied by programmable coefficients by the tap amplifiers
and summed together. One of the taps near the center can be
selected as the main tap. The taps that follow are called postcursor
taps, and the taps that precede are called precursor taps.
By combining different tap values, a wide variety of filter transfer
functions can be created that can, for example, compensate for
the gain or phase distortion of a lossy channel or the chromatic
dispersion of an optical channel.
Tap amplifier gains are controlled using the 2-wire interface
with five bits of magnitude resolution with positive or negative
polarity. To disable a coefficient, set the gain of the particular
tap amplifier to 0 (positive gain sign, and 0 gain setting). In
addition, the tap amplifier can be powered down to save power,
but this may have an impact on the delay and gain of the
remaining taps in the delay chain. See Table 14 to Table 22 and
Table 38 to Table 46 for Array A tap amplifier settings for Channel
0 and Channel 1, respectively. For Array B tap amplifier
settings, see Table 26 to Table 34 and Table 50 to Table 58 for
Channel 0 and Channel 1, respectively.
Each channel has two sets of tap coefficient register arrays
(Channel 0, Array A; Channel 0, Array B; Channel 1, Array A;
and Channel 1, Array B) that can be configured through the
2-wire interface. Register 0x00 to Register 0x08 set the tap
coefficients of Channel 0, Array A. Register 0x20 to Register 0x28
set the tap coefficients of Channel 0, Array B. Register 0x40 to
Register 0x48 set the tap coefficients of Channel 1, Array A.
Register 0x60 to Register 0x68 set the tap coefficients of
Channel 1, Array B. The REGSEL0 and REGSEL1 pins of the
device set the default register array (A or B), determining the
tap coefficients of a particular channel. For example, applying
REGSEL0 = 0 activates Channel 0, Array A; and REGSEL1 = 0
activates Channel 1, Array A. Applying REGSEL0 = 1 activates
Channel 0, Array B; and REGSEL1 = 1 activates Channel 1,
Array B.
Rev. A | Page 11 of 23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet HMC6545.PDF ] | |
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