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PDF CM6502S Data sheet ( Hoja de datos )
| Número de pieza | CM6502S | |
| Descripción | EPA/90+ ZVS-Like PFC CONTROLLER | |
| Fabricantes | Champion Microelectronic | |
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CM6502S (Dynamic Soft PFC)
http://www.championmicro.com.tw
EPA/90+ ZVS-Like PFC CONTROLLER
Design for High Efficient Power Supply at both Full Load and Light Load
GENERAL DESCRIPTION
CM6802S is a ZVS-Like Single PFC and it is designed to
meet 90+ spec. ( total efficiciency). It has the following key
features.
1.) Around 2% efficiency gain when the output load is
below 40% of the full load.
2.) Hold Up time can be increased ~ 30% from the
existing 6800 power supply.
3.) 420V bulk capacitor value can be reduced, and also
PFC boost ripple current can be reduced; therefore,
the boost inductor core size may be reduced.
4.) No Load Consumption can be reduced to 290mW at
270VAC.
5.) The stress over the entire external power device is
reduced and EMI noise reduced.
6.) A PGB function is designed for interfacing to next
stage controller. It has a customer programmable
low threshold PGTHL.
CM6502S is designed to meet the EPA/80+ regulation. With
the proper design, its efficiency of power supply can easily
approach 90+.
FEATURES
Patents Pending
23V Bi-CMOS process.
Designed for EPA/90+efficiency.
Selectable Boost output from 380V to 342V during light
load.
All high voltage resistors can be greater than 5 Mega
ohm (5 Mega to 8 Mega ohm) to improve the no load
consumption.
Rail to rail CMOS Drivers with on, 60 ohm and off, 30
ohm with 17V zeners.
Fast Start-UP Circuit without extra bleed resistor to aid
VCC reaches 13V sooner.
Low start-up current (55uA typ.)
Low operating current (2.5mA typ.)
16.5V VCC shunt regulator
Dynamic Soft PFC to ease the stress of the Power
Device and Ease the EMI-filter design.
PFC Digital Brown Out
Low total harmonic distortion, THD and Power Factor
approaches 1.0.
Average current, continuous or discontinuous boost
leading edge PFC.
Current fed Gain Modulator for improved noise immunity.
Gain Modulator is a constant maximum power limiter.
Brown-out control, over-voltage protection, UVLO, and
soft start, and Reference OK.
Power Fold Back Protection
2008/06/10 Rev. 1.0
Champion Microelectronic Corporation
1
1 page  
CM6502S (Dynamic Soft PFC)
http://www.championmicro.com.tw
EPA/90+ ZVS-Like PFC CONTROLLER
Design for High Efficient Power Supply at both Full Load and Light Load
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply Vcc=+14V, RT = 7.75K kΩ, CT = 1000pF, TA=Operating Temperature
Range (Note 1)
Symbol
Parameter
Test Conditions
PFC Brown Out
VRMS Threshold High
Room Temperature=25℃
VRMS Threshold Low
Room Temperature=25℃
Hysteresis
AC High Light
Sweep Vrms Pin
AC Low Light
Sweep Vrms Pin
Hysteresis
Voltage Error Amplifier (gmv)
Input Voltage Range
Transconductance
VNONINV = VINV, VEAO = 3.75V @ T=25℃
Feedback Reference Voltage Veao = 1.5V VRMS>2.25V
(High)
Input Bias Current
Note 2
Output High Voltage
Output Low Voltage
Sink Current
Source Current
Open Loop Gain
VFB = 3V, VEAO = 6V
VFB = 1.5V, VEAO = 1.5V
DC gain
Power Supply Rejection Ratio 11V < VCC < 16.5V
Current Error Amplifier (gmi)
Input Voltage Range (Isense pin)
Transconductance
VNONINV = VINV, IEAO = 3.75V @ T=25℃
Input Offset Voltage
VEAO=0V, IAC is open
Output High Voltage
Output Low Voltage
CM6502S
Min. Typ.
Max.
Unit
1.19 1.25
1.32
V
0.97 1.05
1.13
V
170 216 260 mV
2.13 2.25
2.36
V
1.66 1.82 V
0.68 0.86 V
0
38 48
2.32 2.39
-1.0
5.8
TBD
30
60
-0.05
6.0
0.1
6.7
70
40
75
3V
58 μ mho
2.44
0.4
TBD
V
μA
V
V
μA
μA
dB
dB
-1.2
50 65
-10
6.8 7.4
0.1
0.7 V
80 μ mho
50 mV
7.7 V
0.4 V
2008/06/10 Rev. 1.0
Champion Microelectronic Corporation
5
5 Page 
CM6502S (Dynamic Soft PFC)
http://www.championmicro.com.tw
EPA/90+ ZVS-Like PFC CONTROLLER
Design for High Efficient Power Supply at both Full Load and Light Load
Vrms Description:
VRMS pin is designed for the following functions:
1. VRMS is used to detect the AC Brown Out (Also, we can
call it PFC brown out.). When VRMS is less than 1.0 V
+/-5%, PFCOUT will be turned off and VEAO will be softly
discharged toward 0 Volt. When VRMS is greater than
1.25V +/-5%, PFCOUT is enable and VEAO is released.
2. VRMS also is used to determine if the AC Line is high line
or it is low line. If VRMS is above 2.25V +/- 5%, IC will
recognize it is high line the. If VRMS is below 2.0V +/-
5%, it is low line. Between 2.0V<=~ Vrms <=~ 2.25V, it
is the hysteresis.
3. At High Line and Light Load, 380V to 342V (Vfb threshold
moves from 2.5V to 2.25V) is prohibited. At Low Line and
Light Load, 380V to 342V (Vfb threshold moves from 2.5V
to 2.25V) is enable. It provides ZVS-Like performance.
4. It is designed to provide the best THD and PF at high line
since the gain is fixed. However, between 2.0V and
2.25V hysteresis region, it could be either way. Usually,
it represents the line voltage between Vin = 151Vac and
Vin =170Vac.
Current Error Amplifier, IEAO
The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost inductor a
linear function of the line voltage. At the inverting input to the
current error amplifier, the output current of the gain modulator
is summed with a current which results from a negative voltage
being impressed upon the ISENSE pin. The negative voltage on
ISENSE represents the sum of all currents flowing in the PFC
circuit, and is typically derived from a current sense resistor in
series with the negative terminal of the input bridge rectifier.
In higher power applications, two current transformers are
sometimes used, one to monitor the IF of the boost diode. As
stated above, the inverting input of the current error amplifier is
a virtual ground. Given this fact, and the arrangement of the
duty cycle modulator polarities internal to the PFC, an increase
in positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on
ISENSE is adequately negative to cancel this increased current.
Similarly, if the gain modulator’s output decreases, the output
duty cycle will decrease, to achieve a less negative voltage on
the ISENSE pin.
PFC Brown Out (PFC Brown Out Comparator)
The PFC Brown Out comparator monitors the Vrms (pin 4)
voltage and inhibits the PFC and PFC error amplifier output,
Veao is pulled down during the Vrms is lower than threshold. If
this voltage on Vrms is less than its nominal 1.25V. Once this
voltage reaches 1.25V, which corresponds to the PFC input
rms is around 88Vac. It is a hysteresis comparator and its
lower threshold is 1V. After PFC Brown Out conditions are
removed, the system will initiate the start up sequence with the
proper soft start rate set by SS (pin 5).
Cycle-By-Cycle Current Limiter and
Selecting RSENSE
The ISENSE pin, as well as being a part of the current
feedback loop, is a direct input to the cycle-by-cycle current
limiter for the PFC section. Should the input voltage at this pin
ever be more negative than –1V, the output of the PFC will be
disabled until the protection flip-flop is reset by the clock pulse
at the start of the next PFC power cycle.
RS is the sensing resistor of the PFC boost converter. During
the steady state, line input current x RSENSE = Imul x 5.7K. Since
the maximum output voltage of the gain modulator is Imul max x
5.7K= 0.8V during the steady state, RSENSE x line input current
will be limited below 0.8V as well. When VEAO reaches
maximum VEAO which is 6V, Isense can reach 0.8V. At 100%
load, VEAO should be around 4.5V and ISENSE average peak
is 0.6V. It will provide the optimal dynamic response +
tolerance of the components.
Therefore, to choose RSENSE, we use the following equation:
RSENSE + RParasitic =0.6V x Vinpeak / (2 x Line Input power)
For example, if the minimum input voltage is 80VAC, and the
maximum input rms power is 200Watt, RSENSE + RParasitic =
(0.6V x 80V x 1.414) / (2 x 200) = 0.169 ohm. The designer
needs to consider the parasitic resistance and the margin of
the power supply and dynamic response. Assume RParasitic = 30
mOhm, RSENSE = 139 mOhm.
PFC OVP
In the CM6502S, PFC OVP comparator serves to protect the
power circuit from being subjected to excessive voltages if the
load should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to VFB. When the voltage
on VFB exceeds 2.79V, the PFC output driver is shut down.
The PWM section will continue to operate. The OVP
comparator has 250mV of hysteresis, and the PFC will not
restart until the voltage at VFB drops below 2.54V. The VFB
power components and the CM6502S are within their safe
operating voltages, but not so low as to interfere with the boost
voltage regulation loop.
2008/06/10 Rev. 1.0
Champion Microelectronic Corporation
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CM6502S.PDF ] | |
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