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PDF IS65WV102416DALL Data sheet ( Hoja de datos )
| Número de pieza | IS65WV102416DALL | |
| Descripción | ULTRA LOW POWER & LOW POWER CMOS STATIC RAM | |
| Fabricantes | ISSI | |
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IS62/65WV102416DALL
IS62/65WV102416DBLL
1Mx16 LOW VOLTAGE,
ULTRA LOW POWER & LOW POWER CMOS STATIC RAM
JANUARY 2015
KEY FEATURES
High-speed access time: 45ns, 55ns.
CMOS low power operation
– 25 µA (typical) CMOS standby
CMOS for optimum speed and power and TTL
compatible interface levels
Single power supply
– 1.65V~1.98V VDD
(IS62/65WV102416DALL)
– 2.2V~3.6V VDD
(IS62/65WV102416DBLL)
Fully static operation: no clock or refresh
required
Industrial and Automotive temperature support
DESCRIPTION
The ISSI IS62/65WV102416DALL,
IS62/65WV102416DBLL are ULTRA LOW POWER
CMOS 16Mbit static RAMs organized as 1M words
by 16 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices. The IS62WV102416DALL/
DBLL and IS65WV102416DALL/DBLL are
packaged in 48-Pin TSOP (TYPE I).
BLOCK DIAGRAM
A0-19
A20
DECODER
I/O0-7
I/O8-14
I/O15
IO15
CONTROL CIRCUIT
, CS2
MEMORY ARRAY
(1024KX16)
(2048KX8)
COLUMN I/O
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
12/12/2014
1
1 page  
IS62/65WV102416DALL
IS62/65WV102416DBLL
ELECTRICAL CHARACTERISTICS
IS62(5)WV102416DALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
VOH
VOL
VIH(1)
VIL(1)
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
IOH = -0.1 mA
IOL = 0.1 mA
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
VDD + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV102416DBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
VOH
Parameter
Output HIGH Voltage
VOL
VIH(1)
VIL(1)
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
ILI Input Leakage
ILO Output Leakage
Test Conditions
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
2.2 ≤ VDD < 2.7
2.7 ≤ VDD ≤ 3.6
2.2 ≤ VDD < 2.7
2.7 ≤ VDD ≤ 3.6
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
2.0
2.4
—
—
1.8
2.2
–0.3
–0.3
–1
–1
Max.
—
—
0.4
0.4
VDD + 0.3
VDD + 0.3
0.6
0.8
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
12/12/2014
5
5 Page 
IS62/65WV102416DALL
IS62/65WV102416DBLL
WRITE CYCLE NO. 3 (
ADDRESS
CONTROLLED:
IS LOW DURING WRITE CYCLE)
tWC
(1) LOW
tSCS1
tHA
tSCS2
CS2
tAW
tPWE
,
DOUT
DIN
tPWB
tSA tHZWE
DATA UNDEFINED(1)
DATA UNDEFINED(1)
HIGH-Z
tSD
tLZWE
tHD
DATA VALID
Notes:
1. If is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous
READ operation will drive IO BUS.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
12/12/2014
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet IS65WV102416DALL.PDF ] | |
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