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PDF EClamp2410P Data sheet ( Hoja de datos )
| Número de pieza | EClamp2410P | |
| Descripción | ESD Protection Device | |
| Fabricantes | Semtech | |
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PROTECTION PRODUCTS - EMIClampTM
Description
The EClampTM2410P is a combination EMI filter and line
termination device with integrated TVS diodes for use on
Multimedia Card interfaces. This state-of-the-art de-
vice utilizes solid-state silicon-avalanche technology for
superior clamping performance and DC electrical char-
acteristics. They have been optimized for protection of
T-Flash/MicroSD interfaces in cellular phones and other
portable electronics.
The device consists of six circuits that include series im-
pedance matching resistors and pull up resistors as re-
quired by the SD specification. TVS diodes are included
on each line for ESD protection. An additional TVS diode
connection is included for protection of the voltage (Vdd)
bus. Termination resistor value of 45 Ohms is included
on the DAT0, DAT1, DAT2, DAT3, CMD, and CLK lines.
Pull up resistors of 15k Ohms are included on DAT0,
DAT1, DAT2, and CMD lines while a 50k Ohm pull up is
inlcuded on the DAT3 line. These may be configured for
devices operating in SD or SPI mode . The TVS diodes
provide effective suppression of ESD voltages in excess
of ±15kV (air discharge) and ±8kV (contact discharge)
per IEC 61000-4-2, level 4.
The EClamp2410P is in a 16-pin, RoHS/WEEE compliant,
SLP4016P16 package. It measures 4.0 x 1.6 x 0.58mm.
The leads are spaced at a pitch of 0.5mm and are fin-
ished with lead-free NiPd.
EClamp2410P
ESD Protection Device
for T-Flash/MicroSD Interfaces
PRELIMINARY
Features
Bidirectional EMI/RFI filtering and line termination
with integrated ESD protection
ESD protection to IEC 61000-4-2 (ESD) Level 4,
±15kV (air), ±8kV (contact)
TVS working voltage: 5V
Termination Resistors: 45Ω
Pull Up Resistors: 15kΩ (3 each) and 50kΩ
Typical Capacitance per Line: 12pF (VR = 2.5V)
Protection and termination for six lines + Vdd
Solid-state technology
Mechanical Characteristics
SLP4016P16 16-pin package
RoHS/WEEE Compliant
Nominal Dimensions: 4.0 x 1.6 x 0.58 mm
Lead Pitch: 0.5mm
Lead finish: NiPd
Marking: Marking Code
Packaging: Tape and Reel per EIA 481
Applications
T-Flash / MicroSD Interfaces
MMC Interfaces
CDMA, GSM, 3G Cell Phones
Pin Configuration
Package Configuration
D AT 1 In 1
D AT0 In
C L K In
R up1
Vd d
C MD In
D AT3 In
D AT2 In
16 D AT1 O u t
D AT0 O u t
C LK Out
R up3
R up2
C MD Out
D AT3 O u t
D AT2 O u t
12
4.00
1.60
0.50 BSC
0.58
Pin Designation (Top View)
Revision 07/20/2006
16 Pin SLP package (Bottom Side View)
Nominal Dimensions in mm
1 www.semtech.com
1 page  
EClamp2410P
PROTECTION PRODUCTS
Applications Information
Device Connection
The EClamp2410P is a microSD/T-Flash interface device
designed for use in cell phones and other portable
electronic devices. The EClamp2410P is comprised of
series and pull up resistors required on the microSD
interface. Each line also includes TVS diodes for ESD
protection. The device may be configured for SD or SPI
mode operation. In SD mode for example, the 15k Ohm
pull up resistors (Rup 1 and Rup 3) are connected to
VDD. In SPI mode pin 4 is not connected (Rup 1) since
these are reserved lines. The 50k Ohm pull up resistor
is used for card detection or SPI mode selection during
power up and is disconnected by the user during regular
data transfer.
The EClamp2410P is in a 16-pin SLP package. Electrical
connection is made to the 16 pins located at the bottom
of the device. The device has a flow through design for
easy layout. Pin connections are noted in Figure 1. A
center tab serves as the ground connection. Recom-
mendations for the ground connection are given below.
Ground Connection Recommendation
Parasitic inductance present in the board layout will
affect the filtering and ESD performance of the device.
Ground loop inductance can be reduced by using mul-
tiple vias to make the connection to the ground plane.
Figure 2 shows the recommended device layout. The
ground pad vias have a diameter of 0.008 inches (0.20
mm) while the two external vias have a diameter of
0.010 inches (0.250mm). The internal vias are spaced
approximately evenly from the center of the pad. The
designer may choose to use more vias with a smaller di-
ameter (such as 0.005 inches or 0.125mm) since chang-
ing the diameter of the via will result in little change in
inductance.
PRELIMINARY
Figure 1 - Pin Identification and Configuration
(Top Side View)
D AT 1 In 1
D AT0 In
C L K In
R up1
Vd d
C MD In
D AT3 In
D AT2 In
16 D AT1 O u t
D AT0 O u t
C LK Out
R up3
R up2
C MD Out
D AT3 O u t
D AT2 O u t
Figure 2 - Recommended Layout using Ground Vias
Layout Guidelines for Optimum ESD Protection
Good circuit board layout is critical not only for signal
integrity, but also for effective suppression of ESD
induced transients. For optimum ESD protection, the
following guidelines are recommended:
Place the device as close to the connector as
possible. This practice restricts ESD coupling into
adjacent traces and reduces parasitic inductance.
The ESD transient return path to ground should be
kept as short as possible. Whenever possible, use
multiple micro vias connected directly from the
device ground pad to the ground plane.
Avoid running critical signals near board edges.
2006 Semtech Corp.
5
www.semtech.com
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| PDF Descargar | [ Datasheet EClamp2410P.PDF ] | |
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