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PDF SiI9233 Data sheet ( Hoja de datos )
| Número de pieza | SiI9233 | |
| Descripción | HDMI Receiver | |
| Fabricantes | Lattice | |
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SiI9233 HDMI Receiver with Repeater, Multi-
channel Audio, and Deep Color Output
Data Sheet
SiI-DS-1032-A
March 2016
1 page  
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Tables
Table 2.1. Summary of Features ...........................................................................................................................................9
Table 3.1. Digital Video Output Formats ............................................................................................................................12
Table 3.2. Default Video Processing ...................................................................................................................................14
Table 3.3. AVI InfoFrame Video Path Details ......................................................................................................................15
Table 3.4. Digital Output Formats Configurable through Auto Output Format Register ...................................................15
Table 3.5. Supported MCLK Frequencies............................................................................................................................16
Table 3.6. Maximum Audio Sampling Frequency for All Video Format Timings ................................................................18
Table 4.1. Calculation of 24/30/36-Bit Output Setup and Hold Times ...............................................................................33
Table 4.2. Calculation of 12/15/18-Bit Output Setup and Hold Times ...............................................................................34
Table 4.3. I2S Setup and Hold Time Calculations ................................................................................................................35
Table 6.1. Translating HDMI Formats to Output Formats ..................................................................................................44
Table 6.2. Output Video Formats .......................................................................................................................................48
Table 6.3. 4:4:4 Mappings ..................................................................................................................................................49
Table 6.4. YC 4:2:2 Separate Sync Pin Mappings ................................................................................................................51
Table 6.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping ...............................................................................52
Table 6.6. YC 4:2:2 Embedded Sync Pin Mappings.............................................................................................................54
Table 6.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping .............................................................................55
Table 6.8. YC Mux 4:2:2 Mappings .....................................................................................................................................57
Table 6.9. YC Mux 4:2:2 Embedded Sync Pin Mapping ......................................................................................................59
Table 6.10. 12/15/18-Bit Output 4:4:4 Mappings ..............................................................................................................61
Table 7.1. Control of the Default I2C Addresses with the CI2CA Pin...................................................................................64
Table 9.1. Maximum Power Domain Currents versus Video Mode....................................................................................66
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
5
5 Page 
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3.1. TMDS Digital Cores
The TMDS Digital core is the latest generation core that supports HDMI v1.3 and the ability to carry 10/12-bit color
depth. The core can receive TMDS data at up to 225 MHz. Each core performs 10-to-8-bit TMDS decoding on the video
data and 10-to-4 bit TMDS decoding on the audio data received from the three TMDS differential data lines along with
a TMDS differential clock. The TMDS core can sense a stopped clock or stopped video and software can put the HDMI
receiver into power-down mode.
3.1.1. Active Port Detection and Selection
Only one port can be active at a time, under control of the HDMI Receiver’s firmware. Active TMDS signaling can arrive
at all ports, but only one has internal circuitry enabled. The firmware in the display controls these states using register
settings.
Other control signals are associated with the TMDS signals on each HDMI port. The HDMI Receiver can monitor the +5V
supply from each attached host. The firmware can poll registers to check on which ports are connected. The firmware
also controls functional connection to one of the four E-DDC buses, enabling one while disabling the others. An
attached host determines the active status of an attached HDMI device by polling the E-DDC bus to the HDMI Receiver.
Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for a complete description of
port detection and selection.
3.2. HDCP Decryption Engine/XOR Mask
The HDCP decryption engine contains all the necessary logic to decrypt the incoming audio and video data. The
decryption process is entirely controlled by the host side microcontroller/microprocessor through a set sequence of
register reads and writes through the DDC channel. Pre-programmed HDCP keys and a Key Selection Vector (KSV)
stored in the on-chip non-volatile memory are used in the decryption process. A resulting calculated value is applied to
an XOR mask during each clock cycle to decrypt the audio/video data.
The SiI9233 also contains all the necessary logic to support full HDCP repeaters. The KSV values of downstream devices
(up to 16 total) are written to the HDMI receiver through the local I2C bus (CSDA/CSCL). As defined in the HDCP
specification, Vi’ is calculated and made available to the host on the DDC bus (DSDA/DSCL).
3.2.1. HDCP Embedded Keys
The SiI9233 HDMI Receiver comes pre-programmed with a set of production HDCP keys stored on-chip in non-volatile
memory. System manufacturers do not need to purchase key sets from the Digital-Content LLC. All purchasing,
programming, and security for the HDCP keys is handled by Lattice Semiconductor. The pre-programmed HDCP keys
provide the highest level of security, as keys cannot be read out of the device after they are programmed. Before
receiving samples of the SiI9233 receiver, customers must sign the HDCP license agreement (www.digital-cp.com) or a
special NDA with Lattice Semiconductor.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SiI9233.PDF ] | |
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