Datasheet SN74LS109A Equivalent ( PDF ) - Data

SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. http:, , onsemi.com MODE SELECT TRUTH TABLE INPUTS OPERATING MODE

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54, 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. LOGIC DIAGRAM SET (SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12) J 2(14) K 3(13)

1. N channel 2. Enhancement mode 3. Logic Level

1. N channel Enhancement mode 2. Logic Level

1. N-Channel Enhancement mode Logic Level dv, dt rated 2. VDS 60 V RDS(on) 5 Ω ID 0.2 A

1. N-Channel Enhancement mode Logic Level dv, dt rated 2. VDS 60 V RDS(on) 5 Ω ID 0.23 A

The SN7101 is integrated a high stability band gap voltage reference, two ORed operational amplifiers and a current source. This IC compares the DC voltage and the current level at the output of a switching power supply to an internal reference.

It provides a feedback through an Opto-coupler to the PWM controller IC in the primary side. The controlled current generator can be used to modify the level of current limitation by offsetting the information coming from the current sensing resistor.

The SN7103 is a monolithic IC that includes one independent op-amp and another op-amp for which the non inverting input is wired to a 2.5V fixed Voltage Reference.