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Datasheet IS61DDPB24M18 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 7 | IS61DDPB24M18 | DDR-IIP (Burst of 2) CIO Synchronous SRAMs 72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs. t of 2) CIO Synchronous SRAMs
(2.5 Cycle Read Latency)
Advanced Information May 2009
Features
• 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Common data input/output bus. • Synchronous pipeline read with self- |
 Integrated Silicon Solution |
 |
| 6 | IS61DDPB24M18A | 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM IS61DDPB24M18A/A1/A2 IS61DDPB22M36A/A1/A2
4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
ADVANCED INFORMATION JULY 2012
FEATURES
DESCRIPTION
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Common I |
Integrated Silicon Solution |
|
| 5 | IS61DDPB24M18A1 | 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM IS61DDPB24M18A/A1/A2 IS61DDPB22M36A/A1/A2
4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
ADVANCED INFORMATION JULY 2012
FEATURES
DESCRIPTION
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Common I |
Integrated Silicon Solution |
|
| 4 | IS61DDPB24M18A2 | 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM IS61DDPB24M18A/A1/A2 IS61DDPB22M36A/A1/A2
4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
ADVANCED INFORMATION JULY 2012
FEATURES
DESCRIPTION
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Common I |
Integrated Silicon Solution |
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