| P/N |
Descripción |
Fabr. |
PDF |
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ADSP-21065 |
DSP Microcomputer
a
SUMMARY High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture Computer (SHARC®) Four Independent Buses for Dual Data, Instruction, and I, O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I, O Peripheral I2S Suppo
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ADSP-21065L |
DSP Microcomputer
a
SUMMARY High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture Computer (SHARC®) Four Independent Buses for Dual Data, Instruction, and I, O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I, O Peripheral I2S Suppo
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Low-cost Sharc / 60 Mhz / 180 Mflops / 3.3v / Floating Point
a
SUMMARY High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture Computer (SHARC®) Four Independent Buses for Dual Data, Instruction, and I, O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I, O Peripheral I2S Suppo
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ADSP-21065LCS-240 |
DSP Microcomputer
a
SUMMARY High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture Computer (SHARC®) Four Independent Buses for Dual Data, Instruction, and I, O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I, O Peripheral I2S Suppo
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ADSP-21065LKCA-240 |
DSP Microcomputer
a
SUMMARY High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture Computer (SHARC®) Four Independent Buses for Dual Data, Instruction, and I, O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I, O Peripheral I2S Suppo
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