Datasheet 74LS75 Equivalent ( PDF ) - Latch

DM74LS75 Quad Latch August 1986 Revised March 2000 DM74LS75 Quad Latch General Description These latches are ideally suited for use as temporary storage for binary information between processing units and input, output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is HIGH, and the Q output will follow the data input as long as the enab

19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 0.05 0° 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0.13 DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 16 9 5.5 1 *0.22 ± 0.05 0.20 ± 0.04 8 0.80 Max 2.20 Max 0.20 7.80 + 0.30 1.15 0° 8° 0.70 ± 0.20 1.27 *0.42 ± 0.08 0.40 ± 0

4-BIT D LATCH The TTL, MSI SN54, 74LS75 and SN54, 74LS77 are latches used as temporary storage for binary information between processing units and input , output or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. When the Enable goes LOW, the information