Datasheet 74LS30 Equivalent ( PDF ) - Gate

SN54, 74LS30 8-INPUT NAND GATE 8-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Ou

DM74LS30 8-Input NAND Gate May 1986 Revised March 2000 DM74LS30 8-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Ordering Code: Order Number DM74LS30M DM74LS30N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 0.05 0° 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 0.30 1.15 0° 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10

54LS30 DM54LS30 DM74LS30 8-Input NAND Gate June 1989 54LS30 DM54LS30 DM74LS30 8-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function Features Y Alternate Military Aerospace device (54LS30) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6360 1 Orde