Datasheet 74LS28 Equivalent ( PDF ) - Buffer

SN54, 74LS28 QUAD 2-INPUT NOR BUFFER QUAD 2-INPUT NOR BUFFER VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperat

SN74LS280 9-Bit Odd, Even Parity Generators, Checkers The SN74LS280 is a Universal 9-Bit Parity Generator , Checker. It features odd , even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The LS280 is designed without the expander input implementation, but the corresponding function is provided by an input at Pin 4 and the absence of any connect

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 0.05 0° 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 0.30 1.15 0° 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10

54LS283 DM54LS283 DM74LS283 4-Bit Binary Adders with Fast Carry June 1989 54LS283 DM54LS283 DM74LS283 4-Bit Binary Adders with Fast Carry General Description These full adders perform the addition of two 4-bit binary numbers The sum (R) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit These adders feature full internal look ahead across all four bits

54, 74284 4 位 x4 位 行二 制乘法器（OC, 生高位 ） 要 明： 54, 74284 集 路的 4 位 x4 位 行二 制乘法器，其主要 特性的典 型 如下（具 家有可能不是完全一至）： 型 54, 74284 tPLH(A到F) 40ns PD 460mW 器件需 54, 74285 配合使用， 生高位 4 位 。 引出端符 ： A0～A3 字 A 入端 B0~B4 字 B 入端 F4~F7 乘 出端 , ST1,, ST2