Datasheet 74HC73 Equivalent ( PDF ) - Flip-flop

74HC73 Dual JK ip- op with reset; negative-edge trigger Rev. 03 12 November 2004 Product data sheet 1. General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is speci ed in compliance with JEDEC standard no. 7A. The 74HC is a dual negative-edge triggered JK ip- op featuring individual J, K, clock (nCP) and reset

74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 5 2 December 2015 Product data sheet 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.