Datasheet 74ACT10 Equivalent ( PDF ) - Gate

74AC08 74ACT08 Quad 2-Input AND Gate November 1988 Revised November 1999 74AC08 74ACT08 Quad 2-Input AND Gate General Description The AC, ACT08 contains four, 2-input AND gates. Features s ICC reduced by 50% on 74AC only s Outputs source, sink 24 mA Ordering Code: Order Number 74AC08SC 74AC08SJ 74AC08MTC 74AC08PC 74ACT08SC 74ACT08MTC 74ACT08PC Package Number M14A M14D MTC14 N14A M14A MTC14 N

74AC10 74ACT10 Triple 3-Input NAND Gate November 1988 Revised February 2005 74AC10 74ACT10 Triple 3-Input NAND Gate General Description The AC, ACT10 contains three, 3-input NAND gates. Features s ICC reduced by 50% on 74AC only s Outputs source, sink 24 mA Ordering Code: Order Number 74AC10SC 74AC10SJ 74AC10MTC 74AC10PC 74AC10PC_NL (Note 1) 74ACT10SC 74ACT10PC Package Number M14A M14D MTC14

54AC 74AC10 74ACT10 Triple 3-Input NAND Gate March 1993 54AC 74AC10 74ACT10 Triple 3-Input NAND Gate General Description The ’AC ’ACT10 contains three 3-input NAND gates Features Y ICC reduced by 50% on 54AC 74AC only Y Outputs source sink 24 mA Y Standard Military Drawing (SMD) ’AC10 5962-87610 Y For Military 54ACT10 device see the 54ACTQ10 Logic Symbol IEEE IEC Connection Diagrams

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop March 2007 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Features - ICC reduced by 50% - Outputs source, sink 24mA - ACT109 has TTL-compatible inputs tm General Description The AC, ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop March 2007 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Features - ICC reduced by 50% - Outputs source, sink 24mA - ACT109 has TTL-compatible inputs tm General Description The AC, ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and