TS68EN360VR33L PDF File ( Datasheet )

Features CPU32+ Processor (4.5 MIPS at 25 MHz) 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32) Background Debug Mode Byte-misaligned Addressing Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits) Up to 32 Address Lines (At Least 28 Always Available) Complete Static Design (0 - 25 MH- Operation) Slave Mode to Disable CPU32+ (Allows Use with External Processors) Multiple QUICCs Can Share One System Bus (One Master) TS68040 Companion Mode Allows QUICC to be a TS680