SN54LS366A PDF File ( Datasheet )

3-STATE HEX BUFFERS These devices are high speed hex buffers with 3-state outputs. They are organized as single 6-bit or 2-bit , 4-bit, with inverting or non-inverting data (D) paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power Schottky loads when the Enable (E) is LOW. When the Output Enable (E) is HIGH, the outputs are forced to a high impedance “off” state. If the outputs of the 3-state devices are tied together, all but one device must be in the high impedance st