MT48LC1M16A1 PDF File ( Datasheet )

16Mb: x16 IT SDRAM SYNCHRONOUS DRAM FEATURES PC100 functionality Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access, precharge 1 Meg x 16 - 512K x 16 x 2 banks architecture with 11 row, 8 column addresses per bank Programmable burst lengths: 1, 2, 4, 8 or full page Auto Precharge Mode, includes CONCURRENT AUTO PRECHARGE Self Refresh and Adaptable Auto