MT48LC128M4A2 PDF File ( Datasheet )

ADVANCE‡ 512Mb: x4, x8, x16 SDRAM SYNCHRONOUS DRAM FEATURES PC100- and PC133-compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access, precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes Self Refresh Mode 64ms, 8,192-cycle refresh LVTTL-compatible inputs a