MT47H16M16 PDF File ( Datasheet )

256Mb: x4, x8, x16 DDR2 SDRAM DDR2 SDRAM Features VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V JEDEC standard 1.8V I, O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Duplicate output strobe (RDQS) option for x8 configuration DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Programmable CAS Latency (CL): 3 and 4 Posted CAS additive latency (AL): 0, 1, 2, 3, and 4 WRITE latency = READ latency - 1