IDT71V2556S PDF File ( Datasheet )

128K x 36, 256K x 18 3.3V Synchronous ZBT™ SRAMs 2.5V I, O, Burst Counter Pipelined Outputs 128K x 36, 256K x 18 memory configurations x Supports high performance system speed - 200 MH- (3.2 ns Clock-to-Data Access) x ZBTTM Feature - No dead cycles between write and read cycles x Internally synchronized output buffer enable eliminates the need to control OE x Single R, W (READ, WRITE) control pin x Positive clock-edge triggered address, data, and control signal registers for fully pipelined a

128K x 36, 256K x 18 3.3V Synchronous ZBT™ SRAMs 2.5V I, O, Burst Counter Pipelined Outputs 128K x 36, 256K x 18 memory configurations x Supports high performance system speed - 200 MH- (3.2 ns Clock-to-Data Access) x ZBTTM Feature - No dead cycles between write and read cycles x Internally synchronized output buffer enable eliminates the need to control OE x Single R, W (READ, WRITE) control pin x Positive clock-edge triggered address, data, and control signal registers for fully pipelined a