HD74ALVCH16500 PDF File ( Datasheet )

HD74ALVCH16500 18-bit Universal Bus Transceivers with 3-state Outputs ADE-205-167A (Z) 2nd. Edition December 1999 Description Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock ( CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch flip