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DM74S112 PDF File ( Datasheet )

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DM74S112N
J-K Flip-Flop, S Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP16

PDF Datasheet
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DM74S112 Description
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a

Fairchild Semiconductor
Fairchild Semiconductor



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