CXL5003M PDF File ( Datasheet )

CXL5003M, P CMOS-CCD 1H Delay Line for PAL Description The CXL5003M, P are general-purpose CMOS-CCD delay line ICs that provide 1H delay time for PAL. Features Low power consumption 110mW (Typ.) Small size package (8-pin SOP, DIP) Low differential gain DG = 3% (Typ.) Input signal amplitude 180 IRE (= 1.28Vp-p, Max.) Low input clock amplitude operation 150mVp-p (Min.) Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits) Functions 848-bit CCD register