CD4042BM PDF File ( Datasheet )

CD4042BM CD4042BC Quad Clocked D Latch March 1988 CD4042BM CD4042BC Quad Clocked D Latch General Description The CD4042BM CD4042BC quad clocked ‘‘D’’ latch is a monolithic complementary MOS (CMOS) integrated circuit constructed with P- and N-channel enhancement mode transistors The outputs Q and Q either latch or follow the data input depending on the clock level which is programmed by the polarity input For polarity e 0 the information present at the data input is transferred to Q and

CD4042BMS December 1992 CMOS Quad Clocked “D” Latch Pinout CD4042BMS TOP VIEW Features High-Voltage Type (20V Rating) Clock Polarity Control Q and Q Outputs Common Clock Low Power TTL Compatible Standardized Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V Maximum Input Current of 1 A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC 5V, 10V and 15V Parametric Ratings Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V