ADSP2184 PDF File ( Datasheet )

a FEATURES PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 20K Bytes of On-Chip RAM, Conf