ADN4668 PDF File ( Datasheet )

3 V LVDS Quad CMOS Differential Line Receiver ADN4668 FUNCTIONAL BLOCK DIAGRAM VCC FEATURES ±15 kV ESD protection on receiver input pins 400 Mbps (200 MHz) switching rates Flow-through pin configuration simplifies PCB layout 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 2.7 ns maximum propagation delay 3.3 V power supply High impedance outputs on power-down Low power design (3 mW quiescent typical) Interoperable with existing 5 V LVDS drivers Accepts small swing