AD9522-5 PDF File ( Datasheet )

Data Sheet FEATURES Low phase noise, phase-locked loop (PLL) Supports external 3.3 V, 5 V voltage controlled oscillator (VCO), VCXO to 2.4 GH- 1 differential or 2 single-ended reference inputs Accepts CMOS, LVPECL, or LVDS references to 250 MH- Accepts 16.62 MH- to 33.3 MH- crystal for reference input Optional reference clock doubler Reference monitoring capability Revertive automatic and manual reference switchover, holdover modes Glitch-free switchover between references Automatic recovery fr