AD9518-1 PDF File ( Datasheet )

Data Sheet FEATURES Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.30 GH- to 2.65 GH- External VCO, VCXO to 2.4 GH- optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover, holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MH- Programmable delays in path to PFD Digital or analog lock detect, selectable 3 pairs of 1.6 GH- LVPECL outputs Each output pair shares a 1-to-32 divider w