AD9142A PDF File ( Datasheet )

Data Sheet Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter AD9142A FEATURES Supports input data rate up to 575 MH- Very small inherent latency variation: <2 DAC clock cycles Proprietary low spurious and distortion design 6-carrier GSM ACLR = 79 dBc at 200 MH- IF SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF Flexible 16-bit LVDS interface Supports word and byte load Data interface DLL Sample error detection and parity Multiple chip synchronization Fixed latency and data generator laten