AD8151 PDF File ( Datasheet )

FEATURES Low cost 33 × 17, fully differential, nonblocking array 3.2 Gbps per port NRZ data rate Wide power supply range: +3.3 V, 3.3 V Low power 425 mA (outputs enabled) 35 mA (outputs disabled) LV PECL- and LV ECL-compatible CMOS, TTL-level control inputs: 3 V to 5 V Low jitter No heat sinks required Drives a backplane directly Programmable output current Optimize termination impedance User-controlled voltage at the load Minimize power dissipation Individual output disable for busing and red