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74F109PC PDF File ( Datasheet )
onsemi
74F109PC
F/fast Series Dual Positive Edge Triggered J-kbar Flip-flop Complementary Output PDIP16
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| 74F109PC Description |
| Dual JK Positive Edge-Triggered Flip-Flop
74F109 Dual JK Positive Edge-Triggered Flip-Flop
April 1988 Revised November 1999
74F109 Dual JK Positive Edge-Triggered Flip-Flop
General Description
The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH leve
 Fairchild Semiconductor |
| Dual JK Positive Edge-Triggered Flip-Flop
54F, 74F109 Dual JK Positive Edge-Triggered Flip-Flop
54F, 74F109
November 1994
54F, 74F109 Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH
 National Semiconductor |
| Related Part Number |
74F676 | 74F258A 74F132 | 74F32 74F241 | 74F374 |
| DataSheet.es | 2020 | Contacto |