(PDF) 74ACT174PC Datasheet - Hex D-Type Flip-Flop with Master Reset

74AC174 74ACT174 Hex D-Type Flip-Flop with Master Reset November 1988 Revised November 1999 74AC174 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description The AC, ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The

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Hex D-Type Flip-Flop with Master Reset

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74ACT174B

HEX D-TYPE FLIP FLOP WITH CLEAR

74ACT174 HEX D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA s s s s s s s s s HIGH SPEED: fMAX = 200 MH- (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 A (MAX.) at TA = 25 oC COMPATIBLE WIT

74ACT174SJ

Hex D-Type Flip-Flop with Master Reset

74AC174 74ACT174 Hex D-Type Flip-Flop with Master Reset November 1988 Revised November 1999 74AC174 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description The AC, ACT174 is a high-spe

74ACT174M

HEX D-TYPE FLIP FLOP WITH CLEAR

74ACT174MTC

Hex D-Type Flip-Flop with Master Reset

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Esta es una página para buscar información de compra e inventario para 74ACT174PC. Para productos compatibles y de reemplazo con 74ACT174PC, descargue la hoja de datos para obtener más detalles.

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2SC1815

Transistor NPN planar epitaxial de silicio para conmutación y amplificadores de frecuencia.
El transistor se divide en cuatro grupos: O, Y, G y L, dependiendo de su ganancia de CC. Se recomienda el transistor PNP ST 2SA1015 como tipo adicional.

Semtech

74ACT174PC Datasheet PDF

PDF 74ACT174PC Flip-flop ( Hoja de datos )

74ACT174PC PDF Descargar

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74ACT174PC	Hex D-Type Flip-Flop with Master Reset 74AC174 74ACT174 Hex D-Type Flip-Flop with Master Reset November 1988 Revised November 1999 74AC174 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description The AC, ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The