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PDF LT1943 Data sheet ( Hoja de datos )
| Número de pieza | LT1943 | |
| Descripción | High Current Quad Output Regulator | |
| Fabricantes | Linear | |
| Logotipo |  |
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LT1943
High Current Quad Output
Regulator for TFT LCD Panels
FEATURES
■ 4 Integrated Switches: 2.4A Buck, 2.6A Boost,
0.35A Boost, 0.35A Inverter (Guaranteed Minimum
Current Limit)
■ Fixed Frequency, Low Noise Outputs
■ Soft-Start for all Outputs
■ Externally Programmable VON Delay
■ Integrated Schottky Diode for VON Output
■ PGOOD Pin for AVDD Output Disconnect
■ 4.5V to 22V Input Voltage Range
■ PanelProtectTM Circuitry Disables VON Upon Fault
■ Available in Thermally Enhanced 28-Lead TSSOP
U
APPLICATIO S
■ Large TFT-LCD Desktop Monitors
■ Flat Panel Televisions
, LTC and LT are registered trademarks of Linear Technology Corporation.
PanelProtect is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
DESCRIPTIO
The LT®1943 quad output adjustable switching regulator
provides power for large TFT LCD panels. The device,
housed in a low profile 28 pin thermally enhanced TSSOP
package, can generate a 3.3V or 5V logic supply along with
the triple output supply required for the TFT LCD panel.
Operating from an input range of 4.5V to 22V, a step-down
regulator provides a low voltage output VLOGIC with up to
2A current. A high-power step-up converter, a lower-
power step-up converter and an inverting converter pro-
vide the three independent output voltages AVDD, VON and
VOFF required by the LCD panel. A high-side PNP provides
delayed turn-on of the VON signal and can handle up to
30mA. Protection circuitry ensures that VON is disabled if
any of the four outputs are more than 10% below the
programmed voltage.
All switchers are synchronized to an internal 1.2MHz
clock, allowing the use of low profile inductors and ce-
ramic capacitors throughout. A current mode architecture
provides excellent transient response. For best flexibility,
all outputs are adjustable. Soft-start is included in all four
channels. A PGOOD pin can drive an optional PMOS pass
device to provide output disconnect for the AVDD output.
TYPICAL APPLICATIO
VOFF
–5.5V
50mA
VIN, 8V TO 20V
2.2µF 44.2k
0.47µF
10µF
10µH
33µH
VLOGIC
3.3V
2A
10.0k
16.2k
10.0k
22µF
SW4
NFB4
10pF 10µH
0.22µF
4.7µH
FB4
BIAS
BOOST
SW1
FB1
VC1
VIN SW3 SW2
FB2
RUN-SS
LT1943
SS-234
CT
PGOOD
VON
E3
FB3
GND
SGND
VC2 VC3
VC4
1µF
10µH
88.7k
10.0k
0.015µF
0.015µF
0.047µF
PGOOD
274k
10.0k
2.2µF
18k
100pF
2.2nF
100pF
2.2nF
6.8k 27k
100pF
680pF
13k
100pF
2.2nF
AVDD
12.2V
500mA
10µF
VON
35V
30mA
0.47µF
Quad Output TFT-LCD Power Supply
1943 TA01
RUN-SS
2V/DIV
VLOGIC
5V/DIV
AVDD
10V/DIV
VOFF
10V/DIV
VE3
20V/DIV
VON
50V/DIV
IIN(AVG)
1A/DIV
Startup Waveforms
5ms/DIV
1943fa
1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS
MINIMUM Input Voltage to Start,
VLOGIC = 3.3V
6.0
TA = 25°C
5.5
5.0
4.5
4.0
3.5
3.0
0
20 40 60 80
LOAD CURRENT (mA)
100
1943 G04
SW3 Current Limit
0.8
0.7
0.6
0.5
0.4
0.3
0.2
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
1943 G07
SW2 VCESAT
600
TA = 25°C
500
400
300
200
100
0
0 0.5 1.0 1.5 2.0 2.5 3.0
SW2 CURRENT (A)
1943 G10
BOOST Pin Current
100
TA = 25°C
80
60
40
20
0
0 0.5 1.0 1.5 2.0 2.5 3.0
SW1 CURRENT (A)
1943 G05
SW4 Current Limit
0.8
0.7
0.6
0.5
0.4
0.3
0.2
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
1943 G08
SW3 VCESAT
500
TA = 25°C
400
300
200
100
0
0 0.1 0.2 0.3 0.4
SW3 CURRENT (A)
1943 G11
LT1943
SW2 Current Limit
5.0
4.5
4.0
3.5
3.0
2.5
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
1943 G06
SW1 VCESAT
600
TA = 25°C
500
400
300
200
100
0
0 0.5 1.0 1.5 2.0 2.5 3.0
SW1 CURRENT (A)
1943 G09
SW4 VCESAT
500
TA = 25°C
400
300
200
100
0
0 0.1 0.2 0.3 0.4
SW4 CURRENT (A)
1943 G12
1943fa
5
5 Page 
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OPERATIO
The control loop for the four switchers is similar. A pulse
from the slave oscillator sets the RS latch and turns on the
internal NPN bipolar power switch. Current in the switch
and the external inductor begins to increase. When this
current exceeds a level determined by the voltage at VC, the
current comparator resets the latch, turning off the switch.
The current in the inductor flows through the Schottky
diode and begins to decrease. The cycle begins again at the
next pulse from the oscillator. In this way, the voltage on
the VC pin controls the current through the inductor to the
output. The internal error amplifier regulates the output
voltage by continually adjusting the VC pin voltage. The
threshold for switching on the VC pin is 0.8V, and an active
clamp of 1.8V limits the output current. The RUN/SS and
SS-234 pins also clamp the VC pin voltage. As the internal
current source charges the external soft-start capacitor,
the current limit increases slowly.
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
This slave oscillator is normally synchronized to the mas-
ter oscillator. A comparator senses when VFB is less than
0.5V and switches the regulator from the master oscillator
to a slower slave oscillator. The VFB pin is less than 0.5V
during startup, short-circuit, and overload conditions.
Frequency foldback helps limit switch current and power
dissipation under these conditions.
The switch driver for SW1 operates either from VIN or from
the BOOST pin. An external capacitor and diode are used
to generate a voltage at the BOOST pin that is higher than
the input supply. This allows the driver to saturate the
internal bipolar NPN power switch for efficient operation.
STEP-DOWN CONSIDERATIONS
FB Resistor Network
The output voltage for switcher 1 is programmed with a
resistor divider (refer to the Block Diagram) between the
output and the FB pin. Choose the resistors according to:
R2 = R1(VOUT/1.25V – 1)
R1 should be 10kΩ or less to avoid bias current errors.
LT1943
Input Voltage Range
The minimum operating voltage of switcher 1 is deter-
mined either by the LT1943’s undervoltage lockout of ~4V,
or by its maximum duty cycle. The duty cycle is the fraction
of time that the internal switch is on and is determined by
the input and output voltages:
DC = (VOUT + VF)/(VIN – VSW + VF)
where VF is the forward voltage drop of the catch diode
(~0.4V) and VSW is the voltage drop of the internal switch
(~0.3V at maximum load). This leads to a minimum input
voltage of
VIN(MIN) = (VOUT + VF)/DCMAX – VF + VSW
with DCMAX = 0.82.
Inductor Selection and Maximum Output Current
A good first choice for the inductor value is:
L = (VOUT + VF)/1.2
where VF is the voltage drop of the catch diode (~0.4V) and
L is in µH. The inductor’s RMS current rating must be
greater than the maximum load current and its saturation
current should be at least 30% higher. For highest effi-
ciency, the series resistance (DCR) should be less than
0.1Ω. Table 1 lists several vendors and types that are
suitable.
The optimum inductor for a given application may differ
from the one indicated by this simple design guide. A
larger value inductor provides a higher maximum load
current, and reduces the output voltage ripple. If your load
is lower than the maximum load current, then you can
relax the value of the inductor and operate with higher
ripple current. This allows you to use a physically smaller
inductor, or one with a lower DCR resulting in higher
efficiency. Be aware that the maximum load current
depends on input voltage. A graph in the Typical Perfor-
mance section of this data sheet shows the maximum load
current as a function of input voltage and inductor value
for VOUT = 3.3V. In addition, low inductance may result in
discontinuous mode operation, which further reduces
1943fa
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LT1943.PDF ] | |
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